src/mainboard/tyan/s2895/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <cpu/amd/model_fxx_rev.h>
  12 #include "northbridge/amd/amdk8/incoherent_ht.c"
  13 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  14 #include "northbridge/amd/amdk8/raminit.h"
  15 #include "cpu/amd/model_fxx/apic_timer.c"
  16 #include "lib/delay.c"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "northbridge/amd/amdk8/reset_test.c"
  19 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  20 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  21 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  22 #define SUPERIO_GPIO_IO_BASE 0x400
  23 #include "cpu/x86/bist.h"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include <cpu/amd/mtrr.h>
  26 #include "cpu/x86/mtrr/earlymtrr.c"
  27 #include "northbridge/amd/amdk8/setup_resource_map.c"
  28 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  29
  30 static void memreset_setup(void)
  31 {
  32 }
  33
  34 static void memreset(int controllers, const struct mem_controller *ctrl)
  35 {
  36 }
  37
  38 static void sio_gpio_setup(void)
  39 {
  40         unsigned value;
  41
  42         /*Enable onboard scsi*/
  43         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  44         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  45         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  46 }
  47
  48 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  49 {
  50         /* nothing to do */
  51 }
  52
  53 static inline int spd_read_byte(unsigned device, unsigned address)
  54 {
  55         return smbus_read_byte(device, address);
  56 }
  57
  58 #include "northbridge/amd/amdk8/raminit.c"
  59 #include "northbridge/amd/amdk8/coherent_ht.c"
  60 #include "lib/generic_sdram.c"
  61
  62  /* tyan does not want the default */
  63 #include "resourcemap.c"
  64
  65 #include "cpu/amd/dualcore/dualcore.c"
  66
  67 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  68
  69 //set GPIO to input mode
  70 #define CK804_MB_SETUP \
  71         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
  72         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
  73         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
  74         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
  75         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
  76         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
  77
  78 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  79
  80 #include "cpu/amd/car/post_cache_as_ram.c"
  81
  82 #include "cpu/amd/model_fxx/init_cpus.c"
  83
  84 #include "northbridge/amd/amdk8/early_ht.c"
  85
  86 static void sio_setup(void)
  87 {
  88         unsigned value;
  89         u32 dword;
  90         u8 byte;
  91
  92         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
  93
  94         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  95         byte |= 0x20;
  96         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  97
  98         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  99         dword |= (1<<29)|(1<<0);
 100         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 101
 102         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
 103         dword |= (1<<16);
 104         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 105
 106         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 107         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 108         value &= 0xbf;
 109         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 110 }
 111
 112 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 113 {
 114         static const u16 spd_addr [] = {
 115                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 116                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 117                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 118                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 119         };
 120
 121         int needs_reset;
 122         unsigned bsp_apicid = 0;
 123
 124         struct mem_controller ctrl[8];
 125         unsigned nodes;
 126
 127         if (!cpu_init_detectedx && boot_cpu()) {
 128                 /* Nothing special needs to be done to find bus 0 */
 129                 /* Allow the HT devices to be found */
 130
 131                 enumerate_ht_chain();
 132
 133                 sio_setup();
 134         }
 135
 136         if (bist == 0) {
 137                 bsp_apicid = init_cpus(cpu_init_detectedx);
 138         }
 139
 140         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 141         uart_init();
 142         console_init();
 143
 144         /* Halt if there was a built in self test failure */
 145         report_bist_failure(bist);
 146
 147         sio_gpio_setup();
 148
 149         setup_mb_resource_map();
 150
 151         needs_reset = setup_coherent_ht_domain();
 152
 153         wait_all_core0_started();
 154
 155         // It is said that we should start core1 after all core0 launched
 156         start_other_cores();
 157         wait_all_other_cores_started(bsp_apicid);
 158
 159         needs_reset |= ht_setup_chains_x();
 160
 161         needs_reset |= ck804_early_setup_x();
 162
 163         if (needs_reset) {
 164                 printk(BIOS_INFO, "ht reset -\n");
 165                 soft_reset();
 166         }
 167
 168         allow_all_aps_stop(bsp_apicid);
 169
 170         nodes = get_nodes();
 171         //It's the time to set ctrl now;
 172         fill_mem_ctrl(nodes, ctrl, spd_addr);
 173
 174         enable_smbus();
 175
 176         memreset_setup();
 177         sdram_initialize(nodes, ctrl);
 178
 179         post_cache_as_ram();
 180 }
 181