3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
8 #include <pc80/mc146818rtc.h>
9 #include <console/console.h>
12 #include <cpu/amd/model_fxx_rev.h>
13 #include "northbridge/amd/amdk8/incoherent_ht.c"
14 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
15 #include "northbridge/amd/amdk8/raminit.h"
16 #include "cpu/amd/model_fxx/apic_timer.c"
17 #include "lib/delay.c"
18 #include "cpu/x86/lapic/boot_cpu.c"
19 #include "northbridge/amd/amdk8/reset_test.c"
20 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
21 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
22 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
23 #define SUPERIO_GPIO_IO_BASE 0x400
24 #include "cpu/x86/bist.h"
25 #include "northbridge/amd/amdk8/debug.c"
26 #include <cpu/amd/mtrr.h>
27 #include "cpu/x86/mtrr/earlymtrr.c"
28 #include "northbridge/amd/amdk8/setup_resource_map.c"
29 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
31 static void memreset_setup(void)
35 static void memreset(int controllers, const struct mem_controller *ctrl)
39 static void sio_gpio_setup(void)
43 /*Enable onboard scsi*/
44 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
45 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
46 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
49 static inline void activate_spd_rom(const struct mem_controller *ctrl)
54 static inline int spd_read_byte(unsigned device, unsigned address)
56 return smbus_read_byte(device, address);
59 #include "northbridge/amd/amdk8/raminit.c"
60 #include "northbridge/amd/amdk8/coherent_ht.c"
61 #include "lib/generic_sdram.c"
62 #include "resourcemap.c" /* tyan does not want the default */
63 #include "cpu/amd/dualcore/dualcore.c"
64 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
66 //set GPIO to input mode
67 #define CK804_MB_SETUP \
68 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
69 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
70 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
71 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
72 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
73 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
75 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
76 #include "cpu/amd/car/post_cache_as_ram.c"
77 #include "cpu/amd/model_fxx/init_cpus.c"
78 #include "northbridge/amd/amdk8/early_ht.c"
80 static void sio_setup(void)
86 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
88 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
90 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
92 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
93 dword |= (1<<29)|(1<<0);
94 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
96 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
98 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
100 lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
101 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
103 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
106 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
108 static const u16 spd_addr [] = {
116 unsigned bsp_apicid = 0;
118 struct mem_controller ctrl[8];
121 if (!cpu_init_detectedx && boot_cpu()) {
122 /* Nothing special needs to be done to find bus 0 */
123 /* Allow the HT devices to be found */
125 enumerate_ht_chain();
131 bsp_apicid = init_cpus(cpu_init_detectedx);
134 lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
138 /* Halt if there was a built in self test failure */
139 report_bist_failure(bist);
143 setup_mb_resource_map();
145 needs_reset = setup_coherent_ht_domain();
147 wait_all_core0_started();
149 // It is said that we should start core1 after all core0 launched
151 wait_all_other_cores_started(bsp_apicid);
153 needs_reset |= ht_setup_chains_x();
155 needs_reset |= ck804_early_setup_x();
158 printk(BIOS_INFO, "ht reset -\n");
162 allow_all_aps_stop(bsp_apicid);
165 //It's the time to set ctrl now;
166 fill_mem_ctrl(nodes, ctrl, spd_addr);
171 sdram_initialize(nodes, ctrl);