src/mainboard/tyan/s2895/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #define K8_ALLOCATE_IO_RANGE 1
   5
   6 #define QRANK_DIMM_SUPPORT 1
   7
   8 #if CONFIG_LOGICAL_CPUS==1
   9 #define SET_NB_CFG_54 1
  10 #endif
  11
  12 #include <stdint.h>
  13 #include <string.h>
  14 #include <device/pci_def.h>
  15 #include <arch/io.h>
  16 #include <device/pnp_def.h>
  17 #include <arch/romcc_io.h>
  18 #include <cpu/x86/lapic.h>
  19 #include "option_table.h"
  20 #include "pc80/mc146818rtc_early.c"
  21
  22 #include "pc80/serial.c"
  23 #include "arch/i386/lib/console.c"
  24 #include "lib/ramtest.c"
  25
  26 #include <cpu/amd/model_fxx_rev.h>
  27
  28 #include "northbridge/amd/amdk8/incoherent_ht.c"
  29 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  30 #include "northbridge/amd/amdk8/raminit.h"
  31 #include "cpu/amd/model_fxx/apic_timer.c"
  32 #include "lib/delay.c"
  33
  34 #include "cpu/x86/lapic/boot_cpu.c"
  35 #include "northbridge/amd/amdk8/reset_test.c"
  36 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  37 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  38 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  39
  40 #define SUPERIO_GPIO_IO_BASE 0x400
  41
  42 #include "cpu/x86/bist.h"
  43
  44 #include "northbridge/amd/amdk8/debug.c"
  45
  46 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  47
  48 #include "northbridge/amd/amdk8/setup_resource_map.c"
  49
  50 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  51
  52 static void memreset_setup(void)
  53 {
  54 }
  55
  56 static void memreset(int controllers, const struct mem_controller *ctrl)
  57 {
  58 }
  59
  60 static void sio_gpio_setup(void){
  61
  62         unsigned value;
  63
  64         /*Enable onboard scsi*/
  65         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  66         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  67         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  68
  69 }
  70
  71 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  72 {
  73         /* nothing to do */
  74 }
  75
  76 static inline int spd_read_byte(unsigned device, unsigned address)
  77 {
  78         return smbus_read_byte(device, address);
  79 }
  80
  81 #include "northbridge/amd/amdk8/raminit.c"
  82 #include "northbridge/amd/amdk8/coherent_ht.c"
  83 #include "lib/generic_sdram.c"
  84
  85  /* tyan does not want the default */
  86 #include "resourcemap.c"
  87
  88 #include "cpu/amd/dualcore/dualcore.c"
  89
  90 #define CK804_NUM 2
  91 #define CK804_USE_NIC 1
  92 #define CK804_USE_ACI 1
  93
  94 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  95
  96 //set GPIO to input mode
  97 #define CK804_MB_SETUP \
  98         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
  99         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 100         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 101         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 102         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 103         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 104
 105 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 106
 107 #include "cpu/amd/car/copy_and_run.c"
 108 #include "cpu/amd/car/post_cache_as_ram.c"
 109
 110 #include "cpu/amd/model_fxx/init_cpus.c"
 111
 112 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 113 #include "northbridge/amd/amdk8/early_ht.c"
 114
 115 static void sio_setup(void)
 116 {
 117
 118         unsigned value;
 119         uint32_t dword;
 120         uint8_t byte;
 121
 122         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 123
 124         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 125         byte |= 0x20;
 126         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 127
 128         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 129         dword |= (1<<29)|(1<<0);
 130         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 131
 132         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
 133         dword |= (1<<16);
 134         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 135
 136         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 137         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 138         value &= 0xbf;
 139         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 140
 141 }
 142
 143 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 144 {
 145         static const uint16_t spd_addr [] = {
 146                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 147                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 148 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 149                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 150                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 151 #endif
 152         };
 153
 154         int needs_reset;
 155         unsigned bsp_apicid = 0;
 156
 157         struct mem_controller ctrl[8];
 158         unsigned nodes;
 159
 160         if (!cpu_init_detectedx && boot_cpu()) {
 161                 /* Nothing special needs to be done to find bus 0 */
 162                 /* Allow the HT devices to be found */
 163
 164                 enumerate_ht_chain();
 165
 166                 sio_setup();
 167
 168                 /* Setup the ck804 */
 169                 ck804_enable_rom();
 170         }
 171
 172         if (bist == 0) {
 173                 bsp_apicid = init_cpus(cpu_init_detectedx);
 174         }
 175
 176 //      post_code(0x32);
 177
 178         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 179         uart_init();
 180         console_init();
 181
 182         /* Halt if there was a built in self test failure */
 183         report_bist_failure(bist);
 184
 185         sio_gpio_setup();
 186
 187         setup_mb_resource_map();
 188
 189         needs_reset = setup_coherent_ht_domain();
 190
 191         wait_all_core0_started();
 192 #if CONFIG_LOGICAL_CPUS==1
 193         // It is said that we should start core1 after all core0 launched
 194         start_other_cores();
 195         wait_all_other_cores_started(bsp_apicid);
 196 #endif
 197
 198         needs_reset |= ht_setup_chains_x();
 199
 200         needs_reset |= ck804_early_setup_x();
 201
 202         if (needs_reset) {
 203                 printk(BIOS_INFO, "ht reset -\n");
 204                 soft_reset();
 205         }
 206
 207         allow_all_aps_stop(bsp_apicid);
 208
 209         nodes = get_nodes();
 210         //It's the time to set ctrl now;
 211         fill_mem_ctrl(nodes, ctrl, spd_addr);
 212
 213         enable_smbus();
 214
 215         memreset_setup();
 216         sdram_initialize(nodes, ctrl);
 217
 218         post_cache_as_ram();
 219 }