src/mainboard/tyan/s2895/romstage.c

   1 #define K8_ALLOCATE_IO_RANGE 1
   2
   3 #define QRANK_DIMM_SUPPORT 1
   4
   5 #if CONFIG_LOGICAL_CPUS==1
   6 #define SET_NB_CFG_54 1
   7 #endif
   8
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <device/pci_def.h>
  12 #include <arch/io.h>
  13 #include <device/pnp_def.h>
  14 #include <arch/romcc_io.h>
  15 #include <cpu/x86/lapic.h>
  16 #include <pc80/mc146818rtc.h>
  17 #include <console/console.h>
  18 #include <lib.h>
  19 #include <cpu/amd/model_fxx_rev.h>
  20 #include "northbridge/amd/amdk8/incoherent_ht.c"
  21 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  22 #include "northbridge/amd/amdk8/raminit.h"
  23 #include "cpu/amd/model_fxx/apic_timer.c"
  24 #include "lib/delay.c"
  25 #include "cpu/x86/lapic/boot_cpu.c"
  26 #include "northbridge/amd/amdk8/reset_test.c"
  27 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  28 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  29 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  30 #define SUPERIO_GPIO_IO_BASE 0x400
  31 #include "cpu/x86/bist.h"
  32 #include "northbridge/amd/amdk8/debug.c"
  33 #include <cpu/amd/mtrr.h>
  34 #include "cpu/x86/mtrr/earlymtrr.c"
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  37
  38 static void memreset_setup(void)
  39 {
  40 }
  41
  42 static void memreset(int controllers, const struct mem_controller *ctrl)
  43 {
  44 }
  45
  46 static void sio_gpio_setup(void)
  47 {
  48         unsigned value;
  49
  50         /*Enable onboard scsi*/
  51         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  52         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  53         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  54 }
  55
  56 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  57 {
  58         /* nothing to do */
  59 }
  60
  61 static inline int spd_read_byte(unsigned device, unsigned address)
  62 {
  63         return smbus_read_byte(device, address);
  64 }
  65
  66 #include "northbridge/amd/amdk8/raminit.c"
  67 #include "northbridge/amd/amdk8/coherent_ht.c"
  68 #include "lib/generic_sdram.c"
  69
  70  /* tyan does not want the default */
  71 #include "resourcemap.c"
  72
  73 #include "cpu/amd/dualcore/dualcore.c"
  74
  75 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  76
  77 //set GPIO to input mode
  78 #define CK804_MB_SETUP \
  79         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
  80         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
  81         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
  82         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
  83         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
  84         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
  85
  86 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  87
  88 #include "cpu/amd/car/post_cache_as_ram.c"
  89
  90 #include "cpu/amd/model_fxx/init_cpus.c"
  91
  92 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  93 #include "northbridge/amd/amdk8/early_ht.c"
  94
  95 static void sio_setup(void)
  96 {
  97         unsigned value;
  98         u32 dword;
  99         u8 byte;
 100
 101         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 102
 103         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 104         byte |= 0x20;
 105         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 106
 107         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 108         dword |= (1<<29)|(1<<0);
 109         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 110
 111         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
 112         dword |= (1<<16);
 113         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 114
 115         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 116         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 117         value &= 0xbf;
 118         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 119 }
 120
 121 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 122 {
 123         static const u16 spd_addr [] = {
 124                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 125                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 126                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 127                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 128         };
 129
 130         int needs_reset;
 131         unsigned bsp_apicid = 0;
 132
 133         struct mem_controller ctrl[8];
 134         unsigned nodes;
 135
 136         if (!cpu_init_detectedx && boot_cpu()) {
 137                 /* Nothing special needs to be done to find bus 0 */
 138                 /* Allow the HT devices to be found */
 139
 140                 enumerate_ht_chain();
 141
 142                 sio_setup();
 143
 144                 /* Setup the ck804 */
 145                 ck804_enable_rom();
 146         }
 147
 148         if (bist == 0) {
 149                 bsp_apicid = init_cpus(cpu_init_detectedx);
 150         }
 151
 152         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 153         uart_init();
 154         console_init();
 155
 156         /* Halt if there was a built in self test failure */
 157         report_bist_failure(bist);
 158
 159         sio_gpio_setup();
 160
 161         setup_mb_resource_map();
 162
 163         needs_reset = setup_coherent_ht_domain();
 164
 165         wait_all_core0_started();
 166
 167         // It is said that we should start core1 after all core0 launched
 168         start_other_cores();
 169         wait_all_other_cores_started(bsp_apicid);
 170
 171         needs_reset |= ht_setup_chains_x();
 172
 173         needs_reset |= ck804_early_setup_x();
 174
 175         if (needs_reset) {
 176                 printk(BIOS_INFO, "ht reset -\n");
 177                 soft_reset();
 178         }
 179
 180         allow_all_aps_stop(bsp_apicid);
 181
 182         nodes = get_nodes();
 183         //It's the time to set ctrl now;
 184         fill_mem_ctrl(nodes, ctrl, spd_addr);
 185
 186         enable_smbus();
 187
 188         memreset_setup();
 189         sdram_initialize(nodes, ctrl);
 190
 191         post_cache_as_ram();
 192 }
 193