src/mainboard/tyan/s2895/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  21 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  22 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  23 #define SUPERIO_GPIO_IO_BASE 0x400
  24 #include "cpu/x86/bist.h"
  25 #include "northbridge/amd/amdk8/debug.c"
  26 #include <cpu/amd/mtrr.h>
  27 #include "cpu/x86/mtrr/earlymtrr.c"
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  30
  31 static void memreset_setup(void)
  32 {
  33 }
  34
  35 static void memreset(int controllers, const struct mem_controller *ctrl)
  36 {
  37 }
  38
  39 static void sio_gpio_setup(void)
  40 {
  41         unsigned value;
  42
  43         /*Enable onboard scsi*/
  44         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  45         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  46         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  47 }
  48
  49 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  50 {
  51         /* nothing to do */
  52 }
  53
  54 static inline int spd_read_byte(unsigned device, unsigned address)
  55 {
  56         return smbus_read_byte(device, address);
  57 }
  58
  59 #include "northbridge/amd/amdk8/raminit.c"
  60 #include "northbridge/amd/amdk8/coherent_ht.c"
  61 #include "lib/generic_sdram.c"
  62
  63  /* tyan does not want the default */
  64 #include "resourcemap.c"
  65
  66 #include "cpu/amd/dualcore/dualcore.c"
  67
  68 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  69
  70 //set GPIO to input mode
  71 #define CK804_MB_SETUP \
  72         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
  73         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
  74         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
  75         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
  76         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
  77         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
  78
  79 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  80
  81 #include "cpu/amd/car/post_cache_as_ram.c"
  82
  83 #include "cpu/amd/model_fxx/init_cpus.c"
  84
  85 #include "northbridge/amd/amdk8/early_ht.c"
  86
  87 static void sio_setup(void)
  88 {
  89         unsigned value;
  90         u32 dword;
  91         u8 byte;
  92
  93         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
  94
  95         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  96         byte |= 0x20;
  97         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  98
  99         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 100         dword |= (1<<29)|(1<<0);
 101         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 102
 103         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
 104         dword |= (1<<16);
 105         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 106
 107         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 108         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 109         value &= 0xbf;
 110         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 111 }
 112
 113 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 114 {
 115         static const u16 spd_addr [] = {
 116                 DIMM0, DIMM2, 0, 0,
 117                 DIMM1, DIMM3, 0, 0,
 118                 DIMM4, DIMM6, 0, 0,
 119                 DIMM5, DIMM7, 0, 0,
 120         };
 121
 122         int needs_reset;
 123         unsigned bsp_apicid = 0;
 124
 125         struct mem_controller ctrl[8];
 126         unsigned nodes;
 127
 128         if (!cpu_init_detectedx && boot_cpu()) {
 129                 /* Nothing special needs to be done to find bus 0 */
 130                 /* Allow the HT devices to be found */
 131
 132                 enumerate_ht_chain();
 133
 134                 sio_setup();
 135         }
 136
 137         if (bist == 0) {
 138                 bsp_apicid = init_cpus(cpu_init_detectedx);
 139         }
 140
 141         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 142         uart_init();
 143         console_init();
 144
 145         /* Halt if there was a built in self test failure */
 146         report_bist_failure(bist);
 147
 148         sio_gpio_setup();
 149
 150         setup_mb_resource_map();
 151
 152         needs_reset = setup_coherent_ht_domain();
 153
 154         wait_all_core0_started();
 155
 156         // It is said that we should start core1 after all core0 launched
 157         start_other_cores();
 158         wait_all_other_cores_started(bsp_apicid);
 159
 160         needs_reset |= ht_setup_chains_x();
 161
 162         needs_reset |= ck804_early_setup_x();
 163
 164         if (needs_reset) {
 165                 printk(BIOS_INFO, "ht reset -\n");
 166                 soft_reset();
 167         }
 168
 169         allow_all_aps_stop(bsp_apicid);
 170
 171         nodes = get_nodes();
 172         //It's the time to set ctrl now;
 173         fill_mem_ctrl(nodes, ctrl, spd_addr);
 174
 175         enable_smbus();
 176
 177         memreset_setup();
 178         sdram_initialize(nodes, ctrl);
 179
 180         post_cache_as_ram();
 181 }
 182