3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
7 #include <device/pci_ids.h>
9 #include <arch/romcc_io.h>
10 #include <cpu/x86/lapic.h>
11 #include "pc80/mc146818rtc_early.c"
13 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
14 #include "northbridge/amd/amdk8/early_ht.c"
15 #include "cpu/x86/lapic/boot_cpu.c"
16 #include "northbridge/amd/amdk8/reset_test.c"
18 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
19 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
21 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
23 #define SUPERIO_GPIO_IO_BASE 0x400
25 static void sio_setup(void)
32 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
34 byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
36 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
38 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
39 dword |= (1<<29)|(1<<0);
40 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
43 lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
45 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
47 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
54 static unsigned long main(unsigned long bist)
57 /* Make cerain my local apic is useable */
61 /* Is this a cpu only reset? */
62 if (cpu_init_detected(nodeid)) {
63 if (last_boot_normal()) {
70 /* Is this a secondary cpu? */
72 if (last_boot_normal()) {
79 /* Nothing special needs to be done to find bus 0 */
80 /* Allow the HT devices to be found */
89 /* Is this a deliberate reset by the bios */
90 if (bios_reset_detected() && last_boot_normal()) {
93 /* This is the primary cpu how should I boot? */
94 else if (do_normal_boot()) {
101 asm volatile ("jmp __normal_image"
103 : "a" (bist) /* inputs */
108 //CPU reset will reset memtroller ???
109 asm volatile ("jmp __cpu_reset"
111 : "a"(bist) /* inputs */