2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
5 * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * ISA portions taken from QEMU acpi-dsdt.dsl.
25 DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
27 #include "northbridge/amd/amdk8/amdk8_util.asl"
29 /* For now only define 2 power states:
30 * - S0 which is fully on
31 * - S5 which is soft off
32 * Any others would involve declaring the wake up methods.
34 Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
35 Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
37 /* Root of the bus hierarchy */
40 /* Top PCI device (CK804) */
43 Name (_HID, EisaId ("PNP0A03"))
57 Method (_CRS, 0, NotSerialized)
59 Name (BUF0, ResourceTemplate ()
62 0x0CF8, // Address Range Minimum
63 0x0CF8, // Address Range Maximum
64 0x01, // Address Alignment
65 0x08, // Address Length
67 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
68 0x0000, // Address Space Granularity
69 0x0000, // Address Range Minimum
70 0x0CF7, // Address Range Maximum
71 0x0000, // Address Translation Offset
72 0x0CF8, // Address Length
75 /* Methods bellow use SSDT to get actual MMIO regs
76 The IO ports are from 0xd00, optionally an VGA,
77 otherwise the info from MMIO is used.
80 Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
81 Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
82 Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
86 /* PCI Routing Table */
87 Name (_PRT, Package () {
88 /* Since source is 0, index is IRQ. */
89 /* in ABCD, A=0, B=1, C=2, D=3 */
90 /* SlotFFFF, ABCD, source, index */
91 Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */
92 Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */
93 Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */
94 Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x14 }, /* 0x2 AUDIO IRQ 20 */
95 Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */
96 Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */
97 Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x15 }, /* 0xa LAN IRQ 21 */
102 Name (_ADR, 0x00090000)
105 Name (_PRT, Package () {
106 Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */
107 Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
108 Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
109 Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
110 Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x13 }, /* 1:05 IEEE-1394 IRQ 19 */
114 /* 2:00 PCIe x16 SB IRQ 18 */
117 Name (_ADR, 0x000e0000)
120 Name (_PRT, Package () {
121 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */
122 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
123 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
124 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
129 Name (_HID, EisaId ("PNP0A05"))
130 Name (_ADR, 0x00010000)
132 /* PS/2 keyboard (seems to be important for WinXP install) */
135 Name (_HID, EisaId ("PNP0303"))
136 Method (_STA, 0, NotSerialized)
140 Method (_CRS, 0, NotSerialized)
142 Name (TMP, ResourceTemplate () {
143 IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
144 IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
154 Name (_HID, EisaId ("PNP0F13"))
155 Method (_STA, 0, NotSerialized)
159 Method (_CRS, 0, NotSerialized)
161 Name (TMP, ResourceTemplate () {
171 Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
172 Method (_STA, 0, NotSerialized)
176 Method (_CRS, 0, NotSerialized)
178 Name (TMP, ResourceTemplate () {
179 FixedIO (0x0378, 0x10)
189 Name (_HID, EisaId ("PNP0B00"))
190 Method (_CRS, 0, NotSerialized)
192 Name (TMP, ResourceTemplate () {
193 FixedIO (0x0070, 0x02)
200 /* Floppy controller */
203 Name (_HID, EisaId ("PNP0700"))
204 Method (_STA, 0, NotSerialized)
208 Method (_CRS, 0, NotSerialized)
210 Name (BUF0, ResourceTemplate () {
211 FixedIO (0x03F0, 0x08)
213 DMA (Compatibility, NotBusMaster, Transfer8) {2}
224 Name (_HID, EisaId ("PNP0A03"))
229 Method (_CRS, 0, NotSerialized)
231 Name (BUF0, ResourceTemplate ()
234 0x0CF8, // Address Range Minimum
235 0x0CF8, // Address Range Maximum
236 0x01, // Address Alignment
237 0x08, // Address Length
240 /* Methods bellow use SSDT to get actual MMIO regs
241 The IO ports are from 0xd00, optionally an VGA,
242 otherwise the info from MMIO is used.
243 \_SB.GXXX(node, link)
245 Concatenate (\_SB.GMEM (0x01, 0x00), BUF0, Local1)
246 Concatenate (\_SB.GIOR (0x01, 0x00), Local1, Local2)
247 Concatenate (\_SB.GWBN (0x01, 0x00), Local2, Local3)
251 /* PCI Routing Table for this root bus */
252 Name (_PRT, Package () {
253 /* Since source is 0, index is IRQ. */
254 /* in ABCD, A=0, B=1, C=2, D=3 */
255 /* SlotFFFF, ABCD, source, index */
256 Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x35 }, /* 0xa LAN IRQ 53 */
259 /* PCIe x16 SB2 IRQ 18 */
262 Name (_ADR, 0x000e0000)
265 Name (_PRT, Package () {
266 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x32 }, /* PCIE IRQ48-IRQ51 */
267 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x33 },
268 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x30 },
269 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x31 },
275 /* AMD 8131 PCI-X tunnel */
278 Name (_HID, EisaId ("PNP0A03"))
283 /* There is no _PRT Here because I don't know what to
284 * put in it. Since the 8131 has its own APIC, it
285 * isn't wired to other IRQs. */
287 Method (_CRS, 0, NotSerialized)
289 Name (BUF0, ResourceTemplate ()
292 0x0CF8, // Address Range Minimum
293 0x0CF8, // Address Range Maximum
294 0x01, // Address Alignment
295 0x08, // Address Length
298 /* Methods bellow use SSDT to get actual MMIO regs
299 The IO ports are from 0xd00, optionally an VGA,
300 otherwise the info from MMIO is used.
301 \_SB.GXXX(node, link)
303 Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1)
304 Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2)
305 Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3)
309 /* Channel A PCIX 133 */
312 Name (_ADR, 0x00000000)
315 Name (_PRT, Package () {
316 Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
317 Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
318 Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1a },
319 Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1b },
323 /* Channel B PCIX 100 */
324 Device (PCXS) /* Slot 4, Onboard SCSI, Slot 5 */
326 Name (_ADR, 0x00010000)
329 Name (_PRT, Package () {
330 Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
331 Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1d },
332 Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1e },
333 Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1f },
334 Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x1e }, /* PCIE IRQ28-IRQ31 shifted 2 */
335 Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x1f },
336 Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1c },
337 Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1d },
338 Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 1 */
339 Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1e },
340 Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1f },
341 Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1c },