1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_USE_FAILOVER_IMAGE
7 uses CONFIG_HAVE_FAILOVER_BOOT
8 uses CONFIG_HAVE_HARD_RESET
9 uses CONFIG_IRQ_SLOT_COUNT
10 uses CONFIG_HAVE_OPTION_TABLE
12 uses CONFIG_MAX_PHYSICAL_CPUS
13 uses CONFIG_LOGICAL_CPUS
16 uses CONFIG_FALLBACK_SIZE
17 uses CONFIG_FAILOVER_SIZE
19 uses CONFIG_ROM_SECTION_SIZE
20 uses CONFIG_ROM_IMAGE_SIZE
21 uses CONFIG_ROM_SECTION_SIZE
22 uses CONFIG_ROM_SECTION_OFFSET
23 uses CONFIG_ROM_PAYLOAD
24 uses CONFIG_ROM_PAYLOAD_START
25 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
26 uses CONFIG_PRECOMPRESSED_PAYLOAD
27 uses CONFIG_PAYLOAD_SIZE
29 uses CONFIG_XIP_ROM_SIZE
30 uses CONFIG_XIP_ROM_BASE
31 uses CONFIG_STACK_SIZE
33 uses CONFIG_USE_OPTION_TABLE
34 uses CONFIG_LB_CKS_RANGE_START
35 uses CONFIG_LB_CKS_RANGE_END
36 uses CONFIG_LB_CKS_LOC
37 uses CONFIG_HAVE_ACPI_TABLES
38 uses CONFIG_HAVE_ACPI_RESUME
39 uses CONFIG_HAVE_LOW_TABLES
41 uses CONFIG_HAVE_SMI_HANDLER
43 uses CONFIG_MAINBOARD_PART_NUMBER
44 uses CONFIG_MAINBOARD_VENDOR
45 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
46 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
47 uses COREBOOT_EXTRA_VERSION
50 uses CONFIG_CROSS_COMPILE
54 uses CONFIG_TTYS0_BAUD
55 uses CONFIG_TTYS0_BASE
57 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
58 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
59 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
60 uses CONFIG_CONSOLE_SERIAL8250
61 uses CONFIG_HAVE_INIT_TIMER
63 uses CONFIG_CONSOLE_VGA
64 uses CONFIG_VGA_ROM_RUN
65 uses CONFIG_PCI_ROM_RUN
66 uses CONFIG_HW_MEM_HOLE_SIZEK
67 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
69 uses CONFIG_USE_DCACHE_RAM
70 uses CONFIG_DCACHE_RAM_BASE
71 uses CONFIG_DCACHE_RAM_SIZE
73 uses CONFIG_USE_PRINTK_IN_CAR
75 uses CONFIG_SERIAL_CPU_INIT
77 uses CONFIG_ENABLE_APIC_EXT_ID
78 uses CONFIG_APIC_ID_OFFSET
79 uses CONFIG_LIFT_BSP_APIC_ID
81 uses CONFIG_HT_CHAIN_UNITID_BASE
82 uses CONFIG_HT_CHAIN_END_UNITID_BASE
83 uses CONFIG_SB_HT_CHAIN_ON_BUS0
84 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
86 uses CONFIG_LB_MEM_TOPK
88 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
89 default CONFIG_ROM_SIZE=1024*1024
92 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
94 #default CONFIG_FALLBACK_SIZE=131072
95 #default CONFIG_FALLBACK_SIZE=0x40000
98 default CONFIG_FALLBACK_SIZE=0x3f000
100 default CONFIG_FAILOVER_SIZE=0x01000
103 default CONFIG_LB_MEM_TOPK=2048
106 ## Build code for the fallback boot
108 default CONFIG_HAVE_FALLBACK_BOOT=1
109 default CONFIG_HAVE_FAILOVER_BOOT=1
112 ## Build code to reset the motherboard from coreboot
114 default CONFIG_HAVE_HARD_RESET=1
119 default CONFIG_HAVE_SMI_HANDLER=0
122 ## Build code to export a programmable irq routing table
124 default CONFIG_HAVE_PIRQ_TABLE=1
125 default CONFIG_IRQ_SLOT_COUNT=11
128 ## Build code to export an x86 MP table
129 ## Useful for specifying IRQ routing values
131 default CONFIG_HAVE_MP_TABLE=1
134 ## Build code to provide ACPI support
136 default CONFIG_HAVE_ACPI_TABLES=1
137 default CONFIG_HAVE_LOW_TABLES=1
138 default CONFIG_MULTIBOOT=0
141 ## Build code to export a CMOS option table
143 default CONFIG_HAVE_OPTION_TABLE=1
146 ## Move the default coreboot cmos range off of AMD RTC registers
148 default CONFIG_LB_CKS_RANGE_START=49
149 default CONFIG_LB_CKS_RANGE_END=122
150 default CONFIG_LB_CKS_LOC=123
153 default CONFIG_CONSOLE_VGA=1
154 default CONFIG_PCI_ROM_RUN=1
155 default CONFIG_VGA_ROM_RUN=1
158 ## Build code for SMP support
159 ## Only worry about 2 micro processors
162 default CONFIG_MAX_CPUS=4
163 default CONFIG_MAX_PHYSICAL_CPUS=2
164 default CONFIG_LOGICAL_CPUS=1
166 default CONFIG_SERIAL_CPU_INIT=0
169 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
171 ##HT Unit ID offset, default is 1, the typical one
172 default CONFIG_HT_CHAIN_UNITID_BASE=0x0
174 ##real SB Unit ID, default is 0x20, mean dont touch it at last
175 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
177 #make the SB HT chain on bus 0, default is not (0)
178 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
180 ##only offset for SB chain?, default is yes(1)
181 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
183 #Opteron K8 1G HT Support
184 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
187 default CONFIG_CONSOLE_VGA=1
188 default CONFIG_PCI_ROM_RUN=1
191 ## enable CACHE_AS_RAM specifics
193 default CONFIG_USE_DCACHE_RAM=1
194 default CONFIG_DCACHE_RAM_BASE=0xcf000
195 default CONFIG_DCACHE_RAM_SIZE=0x1000
196 default CONFIG_USE_INIT=0
198 default CONFIG_ENABLE_APIC_EXT_ID=0
199 default CONFIG_APIC_ID_OFFSET=0x10
200 default CONFIG_LIFT_BSP_APIC_ID=0
204 ## Build code to setup a generic IOAPIC
206 default CONFIG_IOAPIC=1
209 ## Clean up the motherboard id strings
211 default CONFIG_MAINBOARD_PART_NUMBER="s2895"
212 default CONFIG_MAINBOARD_VENDOR="Tyan"
213 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
214 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
217 ### coreboot layout values
220 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
221 default CONFIG_ROM_IMAGE_SIZE = 65536
224 ## Use a small 8K stack
226 default CONFIG_STACK_SIZE=0x2000
229 ## Use a small 16K heap
231 default CONFIG_HEAP_SIZE=0x4000
234 ## Only use the option table in a normal image
236 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
239 ## Coreboot C code runs at this location in RAM
241 default CONFIG_RAMBASE=0x00100000
244 ## Load the payload from the ROM
246 default CONFIG_ROM_PAYLOAD = 1
249 ### Defaults of options that you may want to override in the target config file
253 ## The default compiler
255 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
259 ## Disable the gdb stub by default
261 default CONFIG_GDB_STUB=0
263 default CONFIG_USE_PRINTK_IN_CAR=1
266 ## The Serial Console
269 # To Enable the Serial Console
270 default CONFIG_CONSOLE_SERIAL8250=1
272 ## Select the serial console baud rate
273 default CONFIG_TTYS0_BAUD=115200
274 #default CONFIG_TTYS0_BAUD=57600
275 #default CONFIG_TTYS0_BAUD=38400
276 #default CONFIG_TTYS0_BAUD=19200
277 #default CONFIG_TTYS0_BAUD=9600
278 #default CONFIG_TTYS0_BAUD=4800
279 #default CONFIG_TTYS0_BAUD=2400
280 #default CONFIG_TTYS0_BAUD=1200
282 # Select the serial console base port
283 default CONFIG_TTYS0_BASE=0x3f8
285 # Select the serial protocol
286 # This defaults to 8 data bits, 1 stop bit, and no parity
287 default CONFIG_TTYS0_LCS=0x3
290 ### Select the coreboot loglevel
292 ## EMERG 1 system is unusable
293 ## ALERT 2 action must be taken immediately
294 ## CRIT 3 critical conditions
295 ## ERR 4 error conditions
296 ## WARNING 5 warning conditions
297 ## NOTICE 6 normal but significant condition
298 ## INFO 7 informational
299 ## CONFIG_DEBUG 8 debug-level messages
300 ## SPEW 9 Way too many details
302 ## Request this level of debugging output
303 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
304 ## At a maximum only compile in this level of debugging
305 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
308 ## Select power on after power fail setting
309 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
316 default CONFIG_CBFS=0