1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_USE_FAILOVER_IMAGE
6 uses CONFIG_HAVE_FAILOVER_BOOT
7 uses CONFIG_HAVE_HARD_RESET
8 uses CONFIG_IRQ_SLOT_COUNT
9 uses CONFIG_HAVE_OPTION_TABLE
11 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_LOGICAL_CPUS
15 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_FAILOVER_SIZE
18 uses CONFIG_ROM_SECTION_SIZE
19 uses CONFIG_ROM_IMAGE_SIZE
20 uses CONFIG_ROM_SECTION_SIZE
21 uses CONFIG_ROM_SECTION_OFFSET
22 uses CONFIG_ROM_PAYLOAD
23 uses CONFIG_ROM_PAYLOAD_START
24 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
25 uses CONFIG_PRECOMPRESSED_PAYLOAD
26 uses CONFIG_PAYLOAD_SIZE
28 uses CONFIG_XIP_ROM_SIZE
29 uses CONFIG_XIP_ROM_BASE
30 uses CONFIG_STACK_SIZE
32 uses CONFIG_USE_OPTION_TABLE
33 uses CONFIG_LB_CKS_RANGE_START
34 uses CONFIG_LB_CKS_RANGE_END
35 uses CONFIG_LB_CKS_LOC
36 uses CONFIG_HAVE_ACPI_TABLES
37 uses CONFIG_HAVE_ACPI_RESUME
38 uses CONFIG_HAVE_LOW_TABLES
40 uses CONFIG_HAVE_SMI_HANDLER
42 uses CONFIG_MAINBOARD_PART_NUMBER
43 uses CONFIG_MAINBOARD_VENDOR
44 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
45 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
46 uses COREBOOT_EXTRA_VERSION
49 uses CONFIG_CROSS_COMPILE
53 uses CONFIG_TTYS0_BAUD
54 uses CONFIG_TTYS0_BASE
56 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
57 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
58 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
59 uses CONFIG_CONSOLE_SERIAL8250
60 uses CONFIG_HAVE_INIT_TIMER
62 uses CONFIG_CONSOLE_VGA
63 uses CONFIG_VGA_ROM_RUN
64 uses CONFIG_PCI_ROM_RUN
65 uses CONFIG_HW_MEM_HOLE_SIZEK
66 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
68 uses CONFIG_USE_DCACHE_RAM
69 uses CONFIG_DCACHE_RAM_BASE
70 uses CONFIG_DCACHE_RAM_SIZE
72 uses CONFIG_USE_PRINTK_IN_CAR
74 uses CONFIG_SERIAL_CPU_INIT
76 uses CONFIG_ENABLE_APIC_EXT_ID
77 uses CONFIG_APIC_ID_OFFSET
78 uses CONFIG_LIFT_BSP_APIC_ID
80 uses CONFIG_HT_CHAIN_UNITID_BASE
81 uses CONFIG_HT_CHAIN_END_UNITID_BASE
82 uses CONFIG_SB_HT_CHAIN_ON_BUS0
83 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
85 uses CONFIG_LB_MEM_TOPK
87 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
88 default CONFIG_ROM_SIZE=1024*1024
91 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
95 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
97 default CONFIG_FAILOVER_SIZE=0x01000
100 default CONFIG_LB_MEM_TOPK=2048
103 ## Build code for the fallback boot
105 default CONFIG_HAVE_FALLBACK_BOOT=1
106 default CONFIG_HAVE_FAILOVER_BOOT=1
109 ## Build code to reset the motherboard from coreboot
111 default CONFIG_HAVE_HARD_RESET=1
116 default CONFIG_HAVE_SMI_HANDLER=0
119 ## Build code to export a programmable irq routing table
121 default CONFIG_HAVE_PIRQ_TABLE=1
122 default CONFIG_IRQ_SLOT_COUNT=11
125 ## Build code to export an x86 MP table
126 ## Useful for specifying IRQ routing values
128 default CONFIG_HAVE_MP_TABLE=1
131 ## Build code to provide ACPI support
133 default CONFIG_HAVE_ACPI_TABLES=1
134 default CONFIG_HAVE_LOW_TABLES=1
135 default CONFIG_MULTIBOOT=0
138 ## Build code to export a CMOS option table
140 default CONFIG_HAVE_OPTION_TABLE=1
143 ## Move the default coreboot cmos range off of AMD RTC registers
145 default CONFIG_LB_CKS_RANGE_START=49
146 default CONFIG_LB_CKS_RANGE_END=122
147 default CONFIG_LB_CKS_LOC=123
150 default CONFIG_CONSOLE_VGA=1
151 default CONFIG_PCI_ROM_RUN=1
152 default CONFIG_VGA_ROM_RUN=1
155 ## Build code for SMP support
156 ## Only worry about 2 micro processors
159 default CONFIG_MAX_CPUS=4
160 default CONFIG_MAX_PHYSICAL_CPUS=2
161 default CONFIG_LOGICAL_CPUS=1
163 default CONFIG_SERIAL_CPU_INIT=0
166 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
168 ##HT Unit ID offset, default is 1, the typical one
169 default CONFIG_HT_CHAIN_UNITID_BASE=0x0
171 ##real SB Unit ID, default is 0x20, mean dont touch it at last
172 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
174 #make the SB HT chain on bus 0, default is not (0)
175 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
177 ##only offset for SB chain?, default is yes(1)
178 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
180 #Opteron K8 1G HT Support
181 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
184 default CONFIG_CONSOLE_VGA=1
185 default CONFIG_PCI_ROM_RUN=1
188 ## enable CACHE_AS_RAM specifics
190 default CONFIG_USE_DCACHE_RAM=1
191 default CONFIG_DCACHE_RAM_BASE=0xcf000
192 default CONFIG_DCACHE_RAM_SIZE=0x1000
193 default CONFIG_USE_INIT=0
195 default CONFIG_ENABLE_APIC_EXT_ID=0
196 default CONFIG_APIC_ID_OFFSET=0x10
197 default CONFIG_LIFT_BSP_APIC_ID=0
201 ## Build code to setup a generic IOAPIC
203 default CONFIG_IOAPIC=1
206 ## Clean up the motherboard id strings
208 default CONFIG_MAINBOARD_PART_NUMBER="s2895"
209 default CONFIG_MAINBOARD_VENDOR="Tyan"
210 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
211 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
214 ### coreboot layout values
217 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
218 default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
221 ## Use a small 8K stack
223 default CONFIG_STACK_SIZE=0x2000
226 ## Use a small 16K heap
228 default CONFIG_HEAP_SIZE=0x4000
231 ## Only use the option table in a normal image
233 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
236 ## Coreboot C code runs at this location in RAM
238 default CONFIG_RAMBASE=0x00100000
241 ## Load the payload from the ROM
243 default CONFIG_ROM_PAYLOAD = 1
246 ### Defaults of options that you may want to override in the target config file
250 ## The default compiler
252 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
256 ## Disable the gdb stub by default
258 default CONFIG_GDB_STUB=0
260 default CONFIG_USE_PRINTK_IN_CAR=1
263 ## The Serial Console
266 # To Enable the Serial Console
267 default CONFIG_CONSOLE_SERIAL8250=1
269 ## Select the serial console baud rate
270 default CONFIG_TTYS0_BAUD=115200
271 #default CONFIG_TTYS0_BAUD=57600
272 #default CONFIG_TTYS0_BAUD=38400
273 #default CONFIG_TTYS0_BAUD=19200
274 #default CONFIG_TTYS0_BAUD=9600
275 #default CONFIG_TTYS0_BAUD=4800
276 #default CONFIG_TTYS0_BAUD=2400
277 #default CONFIG_TTYS0_BAUD=1200
279 # Select the serial console base port
280 default CONFIG_TTYS0_BASE=0x3f8
282 # Select the serial protocol
283 # This defaults to 8 data bits, 1 stop bit, and no parity
284 default CONFIG_TTYS0_LCS=0x3
287 ### Select the coreboot loglevel
289 ## EMERG 1 system is unusable
290 ## ALERT 2 action must be taken immediately
291 ## CRIT 3 critical conditions
292 ## ERR 4 error conditions
293 ## WARNING 5 warning conditions
294 ## NOTICE 6 normal but significant condition
295 ## INFO 7 informational
296 ## CONFIG_DEBUG 8 debug-level messages
297 ## SPEW 9 Way too many details
299 ## Request this level of debugging output
300 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
301 ## At a maximum only compile in this level of debugging
302 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
305 ## Select power on after power fail setting
306 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"