1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/failovercalculation.lb
8 ## Build the objects we have code for in this directory.
12 #needed by irq_tables and mptable and acpi_tables
15 if CONFIG_GENERATE_MP_TABLE object mptable.o end
16 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
18 if CONFIG_GENERATE_ACPI_TABLES
21 depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
22 action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
23 action "mv dsdt.hex dsdt.c"
26 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
27 #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
32 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
33 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
37 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
38 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
39 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
40 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
45 ## Build our 16 bit and 32 bit coreboot entry code
47 if CONFIG_HAVE_FAILOVER_BOOT
48 if CONFIG_USE_FAILOVER_IMAGE
49 mainboardinit cpu/x86/16bit/entry16.inc
50 ldscript /cpu/x86/16bit/entry16.lds
53 if CONFIG_USE_FALLBACK_IMAGE
54 mainboardinit cpu/x86/16bit/entry16.inc
55 ldscript /cpu/x86/16bit/entry16.lds
59 mainboardinit cpu/x86/32bit/entry32.inc
62 ldscript /cpu/x86/32bit/entry32.lds
66 ldscript /cpu/amd/car/cache_as_ram.lds
70 ## Build our reset vector (This is where coreboot is entered)
72 if CONFIG_HAVE_FAILOVER_BOOT
73 if CONFIG_USE_FAILOVER_IMAGE
74 mainboardinit cpu/x86/16bit/reset16.inc
75 ldscript /cpu/x86/16bit/reset16.lds
77 mainboardinit cpu/x86/32bit/reset32.inc
78 ldscript /cpu/x86/32bit/reset32.lds
81 if CONFIG_USE_FALLBACK_IMAGE
82 mainboardinit cpu/x86/16bit/reset16.inc
83 ldscript /cpu/x86/16bit/reset16.lds
85 mainboardinit cpu/x86/32bit/reset32.inc
86 ldscript /cpu/x86/32bit/reset32.lds
91 ## Include an id string (For safe flashing)
93 mainboardinit arch/i386/lib/id.inc
94 ldscript /arch/i386/lib/id.lds
97 ## ROMSTRAP table for CK804
99 if CONFIG_HAVE_FAILOVER_BOOT
100 if CONFIG_USE_FAILOVER_IMAGE
101 mainboardinit southbridge/nvidia/ck804/romstrap.inc
102 ldscript /southbridge/nvidia/ck804/romstrap.lds
105 if CONFIG_USE_FALLBACK_IMAGE
106 mainboardinit southbridge/nvidia/ck804/romstrap.inc
107 ldscript /southbridge/nvidia/ck804/romstrap.lds
112 ## Setup Cache-As-Ram
114 mainboardinit cpu/amd/car/cache_as_ram.inc
117 ### This is the early phase of coreboot startup
118 ### Things are delicate and we test to see if we should
119 ### failover to another image.
121 if CONFIG_HAVE_FAILOVER_BOOT
122 if CONFIG_USE_FAILOVER_IMAGE
123 ldscript /arch/i386/lib/failover_failover.lds
126 if CONFIG_USE_FALLBACK_IMAGE
127 ldscript /arch/i386/lib/failover.lds
137 mainboardinit ./auto.inc
141 ## Include the secondary Configuration files
145 include devicetree.cb