src/mainboard/tyan/s2892/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #define QRANK_DIMM_SUPPORT 1
   5
   6 #if CONFIG_LOGICAL_CPUS==1
   7 #define SET_NB_CFG_54 1
   8 #endif
   9
  10 #include <stdint.h>
  11 #include <string.h>
  12 #include <device/pci_def.h>
  13 #include <arch/io.h>
  14 #include <device/pnp_def.h>
  15 #include <arch/romcc_io.h>
  16 #include <cpu/x86/lapic.h>
  17 #include "option_table.h"
  18 #include "pc80/mc146818rtc_early.c"
  19
  20 #include "pc80/serial.c"
  21 #include "arch/i386/lib/console.c"
  22 #include "lib/ramtest.c"
  23
  24 #include <cpu/amd/model_fxx_rev.h>
  25
  26 #include "northbridge/amd/amdk8/incoherent_ht.c"
  27 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  28 #include "northbridge/amd/amdk8/raminit.h"
  29 #include "cpu/amd/model_fxx/apic_timer.c"
  30 #include "lib/delay.c"
  31
  32 #include "cpu/x86/lapic/boot_cpu.c"
  33 #include "northbridge/amd/amdk8/reset_test.c"
  34 #include "northbridge/amd/amdk8/debug.c"
  35 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  36
  37 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  38 #include "cpu/x86/bist.h"
  39
  40 #include "northbridge/amd/amdk8/setup_resource_map.c"
  41
  42 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  43
  44 static void memreset(int controllers, const struct mem_controller *ctrl)
  45 {
  46 }
  47
  48 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  49 {
  50         /* nothing to do */
  51 }
  52
  53 static inline int spd_read_byte(unsigned device, unsigned address)
  54 {
  55         return smbus_read_byte(device, address);
  56 }
  57
  58 #include "northbridge/amd/amdk8/raminit.c"
  59 #include "northbridge/amd/amdk8/coherent_ht.c"
  60 #include "lib/generic_sdram.c"
  61
  62  /* tyan does not want the default */
  63 #include "resourcemap.c"
  64
  65 #include "cpu/amd/dualcore/dualcore.c"
  66
  67 #define CK804_NUM 1
  68 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  69 //set GPIO to input mode
  70 #define CK804_MB_SETUP \
  71         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  72         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  73         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  74         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  75
  76 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  77
  78 #include "cpu/amd/car/copy_and_run.c"
  79
  80 #include "cpu/amd/car/post_cache_as_ram.c"
  81
  82 #include "cpu/amd/model_fxx/init_cpus.c"
  83
  84 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  85 #include "northbridge/amd/amdk8/early_ht.c"
  86
  87 static void sio_setup(void)
  88 {
  89         uint32_t dword;
  90         uint8_t byte;
  91
  92         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  93         byte |= 0x20;
  94         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  95
  96         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  97         dword |= (1<<0);
  98         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  99 }
 100
 101 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 102 {
 103         static const uint16_t spd_addr [] = {
 104                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 105                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 106 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 107                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 108                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 109 #endif
 110         };
 111
 112         int needs_reset;
 113         unsigned bsp_apicid = 0;
 114
 115         struct mem_controller ctrl[8];
 116         unsigned nodes;
 117
 118         if (!cpu_init_detectedx && boot_cpu()) {
 119                 /* Nothing special needs to be done to find bus 0 */
 120                 /* Allow the HT devices to be found */
 121
 122                 enumerate_ht_chain();
 123
 124                 sio_setup();
 125
 126                 /* Setup the ck804 */
 127                 ck804_enable_rom();
 128         }
 129
 130         if (bist == 0) {
 131                 bsp_apicid = init_cpus(cpu_init_detectedx);
 132         }
 133
 134 //      post_code(0x32);
 135
 136         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 137         uart_init();
 138         console_init();
 139
 140         /* Halt if there was a built in self test failure */
 141         report_bist_failure(bist);
 142
 143         setup_mb_resource_map();
 144
 145         needs_reset = setup_coherent_ht_domain();
 146
 147         wait_all_core0_started();
 148 #if CONFIG_LOGICAL_CPUS==1
 149         // It is said that we should start core1 after all core0 launched
 150         start_other_cores();
 151         wait_all_other_cores_started(bsp_apicid);
 152 #endif
 153
 154         needs_reset |= ht_setup_chains_x();
 155
 156         needs_reset |= ck804_early_setup_x();
 157
 158         if (needs_reset) {
 159                 printk(BIOS_INFO, "ht reset -\n");
 160                 soft_reset();
 161         }
 162
 163         allow_all_aps_stop(bsp_apicid);
 164
 165         nodes = get_nodes();
 166         //It's the time to set ctrl now;
 167         fill_mem_ctrl(nodes, ctrl, spd_addr);
 168
 169         enable_smbus();
 170
 171         sdram_initialize(nodes, ctrl);
 172
 173         post_cache_as_ram();
 174 }