src/mainboard/tyan/s2892/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9
  10 #include <console/console.h>
  11 #include <lib.h>
  12 #include <spd.h>
  13
  14 #include <cpu/amd/model_fxx_rev.h>
  15
  16 #include "northbridge/amd/amdk8/incoherent_ht.c"
  17 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "lib/delay.c"
  21
  22 #include "cpu/x86/lapic/boot_cpu.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  26
  27 #include "cpu/x86/mtrr/earlymtrr.c"
  28 #include "cpu/x86/bist.h"
  29
  30 #include "northbridge/amd/amdk8/setup_resource_map.c"
  31
  32 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  33
  34 static void memreset(int controllers, const struct mem_controller *ctrl)
  35 {
  36 }
  37
  38 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  39 {
  40         /* nothing to do */
  41 }
  42
  43 static inline int spd_read_byte(unsigned device, unsigned address)
  44 {
  45         return smbus_read_byte(device, address);
  46 }
  47
  48 #include "northbridge/amd/amdk8/raminit.c"
  49 #include "northbridge/amd/amdk8/coherent_ht.c"
  50 #include "lib/generic_sdram.c"
  51
  52  /* tyan does not want the default */
  53 #include "resourcemap.c"
  54
  55 #include "cpu/amd/dualcore/dualcore.c"
  56
  57 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  58 //set GPIO to input mode
  59 #define CK804_MB_SETUP \
  60         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  61         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  62         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  63         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  64
  65 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  66
  67
  68
  69 #include "cpu/amd/car/post_cache_as_ram.c"
  70
  71 #include "cpu/amd/model_fxx/init_cpus.c"
  72
  73 #include "northbridge/amd/amdk8/early_ht.c"
  74
  75 static void sio_setup(void)
  76 {
  77         uint32_t dword;
  78         uint8_t byte;
  79
  80         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  81         byte |= 0x20;
  82         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  83
  84         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  85         dword |= (1<<0);
  86         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  87 }
  88
  89 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  90 {
  91         static const uint16_t spd_addr [] = {
  92                 DIMM0, DIMM2, 0, 0,
  93                 DIMM1, DIMM3, 0, 0,
  94 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  95                 DIMM4, DIMM6, 0, 0,
  96                 DIMM5, DIMM7, 0, 0,
  97 #endif
  98         };
  99
 100         int needs_reset;
 101         unsigned bsp_apicid = 0;
 102
 103         struct mem_controller ctrl[8];
 104         unsigned nodes;
 105
 106         if (!cpu_init_detectedx && boot_cpu()) {
 107                 /* Nothing special needs to be done to find bus 0 */
 108                 /* Allow the HT devices to be found */
 109
 110                 enumerate_ht_chain();
 111
 112                 sio_setup();
 113         }
 114
 115         if (bist == 0) {
 116                 bsp_apicid = init_cpus(cpu_init_detectedx);
 117         }
 118
 119 //      post_code(0x32);
 120
 121         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 122         uart_init();
 123         console_init();
 124
 125         /* Halt if there was a built in self test failure */
 126         report_bist_failure(bist);
 127
 128         setup_mb_resource_map();
 129
 130         needs_reset = setup_coherent_ht_domain();
 131
 132         wait_all_core0_started();
 133 #if CONFIG_LOGICAL_CPUS==1
 134         // It is said that we should start core1 after all core0 launched
 135         start_other_cores();
 136         wait_all_other_cores_started(bsp_apicid);
 137 #endif
 138
 139         needs_reset |= ht_setup_chains_x();
 140
 141         needs_reset |= ck804_early_setup_x();
 142
 143         if (needs_reset) {
 144                 printk(BIOS_INFO, "ht reset -\n");
 145                 soft_reset();
 146         }
 147
 148         allow_all_aps_stop(bsp_apicid);
 149
 150         nodes = get_nodes();
 151         //It's the time to set ctrl now;
 152         fill_mem_ctrl(nodes, ctrl, spd_addr);
 153
 154         enable_smbus();
 155
 156         sdram_initialize(nodes, ctrl);
 157
 158         post_cache_as_ram();
 159 }
 160