src/mainboard/tyan/s2892/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  22 #include "cpu/x86/mtrr/earlymtrr.c"
  23 #include "cpu/x86/bist.h"
  24 #include "northbridge/amd/amdk8/setup_resource_map.c"
  25
  26 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  27
  28 static void memreset(int controllers, const struct mem_controller *ctrl)
  29 {
  30 }
  31
  32 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  33 {
  34         /* nothing to do */
  35 }
  36
  37 static inline int spd_read_byte(unsigned device, unsigned address)
  38 {
  39         return smbus_read_byte(device, address);
  40 }
  41
  42 #include "northbridge/amd/amdk8/raminit.c"
  43 #include "northbridge/amd/amdk8/coherent_ht.c"
  44 #include "lib/generic_sdram.c"
  45 #include "resourcemap.c" /* tyan does not want the default */
  46 #include "cpu/amd/dualcore/dualcore.c"
  47 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  48
  49 //set GPIO to input mode
  50 #define CK804_MB_SETUP \
  51         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  52         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  53         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  54         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  55
  56 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  57 #include "cpu/amd/car/post_cache_as_ram.c"
  58 #include "cpu/amd/model_fxx/init_cpus.c"
  59 #include "northbridge/amd/amdk8/early_ht.c"
  60
  61 static void sio_setup(void)
  62 {
  63         uint32_t dword;
  64         uint8_t byte;
  65
  66         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  67         byte |= 0x20;
  68         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  69
  70         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  71         dword |= (1<<0);
  72         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  73 }
  74
  75 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  76 {
  77         static const uint16_t spd_addr [] = {
  78                 DIMM0, DIMM2, 0, 0,
  79                 DIMM1, DIMM3, 0, 0,
  80 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  81                 DIMM4, DIMM6, 0, 0,
  82                 DIMM5, DIMM7, 0, 0,
  83 #endif
  84         };
  85
  86         int needs_reset;
  87         unsigned bsp_apicid = 0;
  88
  89         struct mem_controller ctrl[8];
  90         unsigned nodes;
  91
  92         if (!cpu_init_detectedx && boot_cpu()) {
  93                 /* Nothing special needs to be done to find bus 0 */
  94                 /* Allow the HT devices to be found */
  95
  96                 enumerate_ht_chain();
  97
  98                 sio_setup();
  99         }
 100
 101         if (bist == 0) {
 102                 bsp_apicid = init_cpus(cpu_init_detectedx);
 103         }
 104
 105 //      post_code(0x32);
 106
 107         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 108         uart_init();
 109         console_init();
 110
 111         /* Halt if there was a built in self test failure */
 112         report_bist_failure(bist);
 113
 114         setup_mb_resource_map();
 115
 116         needs_reset = setup_coherent_ht_domain();
 117
 118         wait_all_core0_started();
 119 #if CONFIG_LOGICAL_CPUS==1
 120         // It is said that we should start core1 after all core0 launched
 121         start_other_cores();
 122         wait_all_other_cores_started(bsp_apicid);
 123 #endif
 124
 125         needs_reset |= ht_setup_chains_x();
 126
 127         needs_reset |= ck804_early_setup_x();
 128
 129         if (needs_reset) {
 130                 printk(BIOS_INFO, "ht reset -\n");
 131                 soft_reset();
 132         }
 133
 134         allow_all_aps_stop(bsp_apicid);
 135
 136         nodes = get_nodes();
 137         //It's the time to set ctrl now;
 138         fill_mem_ctrl(nodes, ctrl, spd_addr);
 139
 140         enable_smbus();
 141
 142         sdram_initialize(nodes, ctrl);
 143
 144         post_cache_as_ram();
 145 }
 146