6 #include <device/pci_def.h>
8 #include <device/pnp_def.h>
9 #include <arch/romcc_io.h>
10 #include <cpu/x86/lapic.h>
11 #include "option_table.h"
12 #include "pc80/mc146818rtc_early.c"
13 #include "pc80/serial.c"
14 #include "arch/i386/lib/console.c"
15 #include "ram/ramtest.c"
17 #include <cpu/amd/model_fxx_rev.h>
19 #include "northbridge/amd/amdk8/incoherent_ht.c"
20 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
21 #include "northbridge/amd/amdk8/raminit.h"
22 #include "cpu/amd/model_fxx/apic_timer.c"
23 #include "lib/delay.c"
25 #include "cpu/x86/lapic/boot_cpu.c"
26 #include "northbridge/amd/amdk8/reset_test.c"
27 #include "northbridge/amd/amdk8/debug.c"
28 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
30 #include "cpu/amd/mtrr/amd_earlymtrr.c"
31 #include "cpu/x86/bist.h"
33 #include "northbridge/amd/amdk8/setup_resource_map.c"
35 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
37 static void memreset_setup(void)
41 static void memreset(int controllers, const struct mem_controller *ctrl)
45 static inline void activate_spd_rom(const struct mem_controller *ctrl)
50 static inline int spd_read_byte(unsigned device, unsigned address)
52 return smbus_read_byte(device, address);
55 #define QRANK_DIMM_SUPPORT 1
57 #include "northbridge/amd/amdk8/raminit.c"
58 #include "northbridge/amd/amdk8/coherent_ht.c"
59 #include "sdram/generic_sdram.c"
61 /* tyan does not want the default */
62 #include "resourcemap.c"
64 #if CONFIG_LOGICAL_CPUS==1
65 #define SET_NB_CFG_54 1
67 #include "cpu/amd/dualcore/dualcore.c"
70 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
71 //set GPIO to input mode
72 #define CK804_MB_SETUP \
73 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
74 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
75 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
76 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
78 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
80 #include "cpu/amd/car/copy_and_run.c"
82 #include "cpu/amd/car/post_cache_as_ram.c"
84 #include "cpu/amd/model_fxx/init_cpus.c"
86 #if USE_FALLBACK_IMAGE == 1
88 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
89 #include "northbridge/amd/amdk8/early_ht.c"
91 static void sio_setup(void)
96 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
98 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
100 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
102 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
105 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
107 unsigned last_boot_normal_x = last_boot_normal();
109 /* Is this a cpu only reset? or Is this a secondary cpu? */
110 if ((cpu_init_detectedx) || (!boot_cpu())) {
111 if (last_boot_normal_x) {
118 /* Nothing special needs to be done to find bus 0 */
119 /* Allow the HT devices to be found */
121 enumerate_ht_chain();
125 /* Setup the ck804 */
128 /* Is this a deliberate reset by the bios */
130 if (bios_reset_detected() && last_boot_normal_x) {
133 /* This is the primary cpu how should I boot? */
134 else if (do_normal_boot()) {
142 __asm__ volatile ("jmp __normal_image"
144 : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
153 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
155 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
158 #if USE_FALLBACK_IMAGE == 1
159 failover_process(bist, cpu_init_detectedx);
161 real_main(bist, cpu_init_detectedx);
165 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
167 static const uint16_t spd_addr [] = {
168 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
169 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
170 #if CONFIG_MAX_PHYSICAL_CPUS > 1
171 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
172 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
177 unsigned bsp_apicid = 0;
179 struct mem_controller ctrl[8];
183 init_cpus(cpu_init_detectedx);
188 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
192 /* Halt if there was a built in self test failure */
193 report_bist_failure(bist);
195 setup_s2892_resource_map();
197 dump_pci_device(PCI_DEV(0, 0x18, 0));
198 dump_pci_device(PCI_DEV(0, 0x19, 0));
201 needs_reset = setup_coherent_ht_domain();
203 wait_all_core0_started();
204 #if CONFIG_LOGICAL_CPUS==1
205 // It is said that we should start core1 after all core0 launched
207 wait_all_other_cores_started(bsp_apicid);
210 needs_reset |= ht_setup_chains_x();
212 needs_reset |= ck804_early_setup_x();
215 print_info("ht reset -\r\n");
219 allow_all_aps_stop(bsp_apicid);
222 //It's the time to set ctrl now;
223 fill_mem_ctrl(nodes, ctrl, spd_addr);
227 dump_spd_registers(&cpu[0]);
230 dump_smbus_registers();
234 sdram_initialize(nodes, ctrl);