1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_PAYLOAD_SIZE
25 uses CONFIG_XIP_ROM_SIZE
26 uses CONFIG_XIP_ROM_BASE
27 uses CONFIG_STACK_SIZE
29 uses CONFIG_USE_OPTION_TABLE
30 uses CONFIG_LB_CKS_RANGE_START
31 uses CONFIG_LB_CKS_RANGE_END
32 uses CONFIG_LB_CKS_LOC
33 uses CONFIG_HAVE_ACPI_TABLES
34 uses CONFIG_HAVE_ACPI_RESUME
35 uses CONFIG_HAVE_LOW_TABLES
37 uses CONFIG_HAVE_SMI_HANDLER
39 uses CONFIG_MAINBOARD_PART_NUMBER
40 uses CONFIG_MAINBOARD_VENDOR
41 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
42 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
43 uses COREBOOT_EXTRA_VERSION
46 uses CONFIG_CROSS_COMPILE
50 uses CONFIG_TTYS0_BAUD
51 uses CONFIG_TTYS0_BASE
53 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
54 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
55 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
56 uses CONFIG_CONSOLE_SERIAL8250
57 uses CONFIG_CONSOLE_BTEXT
58 uses CONFIG_HAVE_INIT_TIMER
60 uses CONFIG_CONSOLE_VGA
61 uses CONFIG_VGA_ROM_RUN
62 uses CONFIG_PCI_ROM_RUN
63 uses CONFIG_HW_MEM_HOLE_SIZEK
65 uses CONFIG_USE_DCACHE_RAM
66 uses CONFIG_DCACHE_RAM_BASE
67 uses CONFIG_DCACHE_RAM_SIZE
69 uses CONFIG_USE_PRINTK_IN_CAR
71 uses CONFIG_HT_CHAIN_UNITID_BASE
72 uses CONFIG_HT_CHAIN_END_UNITID_BASE
73 uses CONFIG_SB_HT_CHAIN_ON_BUS0
74 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
76 uses CONFIG_LB_MEM_TOPK
78 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
79 default CONFIG_ROM_SIZE=1024*1024
82 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
84 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
91 ## Build code for the fallback boot
93 default CONFIG_HAVE_FALLBACK_BOOT=1
96 ## Build code to reset the motherboard from coreboot
98 default CONFIG_HAVE_HARD_RESET=1
103 default CONFIG_HAVE_SMI_HANDLER=0
106 ## Build code to export a programmable irq routing table
108 default CONFIG_HAVE_PIRQ_TABLE=1
109 default CONFIG_IRQ_SLOT_COUNT=11
112 ## Build code to export an x86 MP table
113 ## Useful for specifying IRQ routing values
115 default CONFIG_HAVE_MP_TABLE=1
118 ## Build code to provide ACPI support
120 default CONFIG_HAVE_ACPI_TABLES=1
121 default CONFIG_HAVE_LOW_TABLES=1
122 default CONFIG_MULTIBOOT=0
125 ## Build code to export a CMOS option table
127 default CONFIG_HAVE_OPTION_TABLE=1
130 ## Move the default coreboot cmos range off of AMD RTC registers
132 default CONFIG_LB_CKS_RANGE_START=49
133 default CONFIG_LB_CKS_RANGE_END=122
134 default CONFIG_LB_CKS_LOC=123
137 default CONFIG_CONSOLE_VGA=1
138 default CONFIG_PCI_ROM_RUN=1
139 default CONFIG_VGA_ROM_RUN=1
142 ## Build code for SMP support
143 ## Only worry about 2 micro processors
146 default CONFIG_MAX_CPUS=4
147 default CONFIG_MAX_PHYSICAL_CPUS=2
148 default CONFIG_LOGICAL_CPUS=1
151 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
153 ##HT Unit ID offset, default is 1, the typical one
154 default CONFIG_HT_CHAIN_UNITID_BASE=0x0
156 ##real SB Unit ID, default is 0x20, mean dont touch it at last
157 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
159 #make the SB HT chain on bus 0, default is not (0)
160 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
162 ##only offset for SB chain?, default is yes(1)
163 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
166 #default CONFIG_CONSOLE_BTEXT=1
169 default CONFIG_CONSOLE_VGA=1
170 default CONFIG_PCI_ROM_RUN=1
173 ## enable CACHE_AS_RAM specifics
175 default CONFIG_USE_DCACHE_RAM=1
176 default CONFIG_DCACHE_RAM_BASE=0xcf000
177 default CONFIG_DCACHE_RAM_SIZE=0x1000
178 default CONFIG_USE_INIT=0
182 ## Build code to setup a generic IOAPIC
184 default CONFIG_IOAPIC=1
187 ## Clean up the motherboard id strings
189 default CONFIG_MAINBOARD_PART_NUMBER="s2892"
190 default CONFIG_MAINBOARD_VENDOR="Tyan"
191 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
192 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892
195 ### coreboot layout values
198 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
199 default CONFIG_ROM_IMAGE_SIZE = 65536
202 ## Use a small 8K stack
204 default CONFIG_STACK_SIZE=0x2000
207 ## Use a small 16K heap
209 default CONFIG_HEAP_SIZE=0x4000
212 ## Only use the option table in a normal image
214 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
217 ## Coreboot C code runs at this location in RAM
219 default CONFIG_RAMBASE=0x00004000
222 ## Load the payload from the ROM
224 default CONFIG_ROM_PAYLOAD = 1
227 ### Defaults of options that you may want to override in the target config file
231 ## The default compiler
233 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
237 ## Disable the gdb stub by default
239 default CONFIG_GDB_STUB=0
241 default CONFIG_USE_PRINTK_IN_CAR=1
244 ## The Serial Console
247 # To Enable the Serial Console
248 default CONFIG_CONSOLE_SERIAL8250=1
250 ## Select the serial console baud rate
251 default CONFIG_TTYS0_BAUD=115200
252 #default CONFIG_TTYS0_BAUD=57600
253 #default CONFIG_TTYS0_BAUD=38400
254 #default CONFIG_TTYS0_BAUD=19200
255 #default CONFIG_TTYS0_BAUD=9600
256 #default CONFIG_TTYS0_BAUD=4800
257 #default CONFIG_TTYS0_BAUD=2400
258 #default CONFIG_TTYS0_BAUD=1200
260 # Select the serial console base port
261 default CONFIG_TTYS0_BASE=0x3f8
263 # Select the serial protocol
264 # This defaults to 8 data bits, 1 stop bit, and no parity
265 default CONFIG_TTYS0_LCS=0x3
268 ### Select the coreboot loglevel
270 ## EMERG 1 system is unusable
271 ## ALERT 2 action must be taken immediately
272 ## CRIT 3 critical conditions
273 ## ERR 4 error conditions
274 ## WARNING 5 warning conditions
275 ## NOTICE 6 normal but significant condition
276 ## INFO 7 informational
277 ## CONFIG_DEBUG 8 debug-level messages
278 ## SPEW 9 Way too many details
280 ## Request this level of debugging output
281 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
282 ## At a maximum only compile in this level of debugging
283 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
286 ## Select power on after power fail setting
287 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"