src/mainboard/tyan/s2891/romstage.c

   1 #if CONFIG_LOGICAL_CPUS==1
   2 #define SET_NB_CFG_54 1
   3 #endif
   4
   5 #include <stdint.h>
   6 #include <string.h>
   7 #include <device/pci_def.h>
   8 #include <arch/io.h>
   9 #include <device/pnp_def.h>
  10 #include <arch/romcc_io.h>
  11 #include <cpu/x86/lapic.h>
  12 #include <pc80/mc146818rtc.h>
  13 #include <console/console.h>
  14 #include <lib.h>
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23 #include "cpu/x86/lapic/boot_cpu.c"
  24 #include "northbridge/amd/amdk8/reset_test.c"
  25 #include "northbridge/amd/amdk8/debug.c"
  26 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  27
  28 #include "cpu/x86/mtrr/earlymtrr.c"
  29 #include "cpu/x86/bist.h"
  30
  31 #include "northbridge/amd/amdk8/setup_resource_map.c"
  32
  33 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  34
  35 static void memreset_setup(void)
  36 {
  37 }
  38
  39 static void memreset(int controllers, const struct mem_controller *ctrl)
  40 {
  41 }
  42
  43 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  44 {
  45         /* nothing to do */
  46 }
  47
  48 static inline int spd_read_byte(unsigned device, unsigned address)
  49 {
  50         return smbus_read_byte(device, address);
  51 }
  52
  53 #include "northbridge/amd/amdk8/raminit.c"
  54 #include "northbridge/amd/amdk8/coherent_ht.c"
  55 #include "lib/generic_sdram.c"
  56
  57  /* tyan does not want the default */
  58 #include "resourcemap.c"
  59
  60 #include "cpu/amd/dualcore/dualcore.c"
  61
  62 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  63 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  64
  65 #include "cpu/amd/car/post_cache_as_ram.c"
  66
  67 #include "cpu/amd/model_fxx/init_cpus.c"
  68
  69 #include "northbridge/amd/amdk8/early_ht.c"
  70
  71 static void sio_setup(void)
  72 {
  73         uint32_t dword;
  74         uint8_t byte;
  75
  76         /* subject decoding*/
  77         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  78         byte |= 0x20;
  79         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  80
  81         /* LPC Positive Decode 0 */
  82         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  83         /* Serial 0, Serial 1 */
  84         dword |= (1<<0) | (1<<1);
  85         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  86
  87 #if 1
  88         /* s2891 has onboard LPC port 80 */
  89         /*Hope I can enable port 80 here
  90         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
  91         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
  92         dword |= (1<<16);
  93         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
  94 #endif
  95 }
  96
  97 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  98 {
  99         static const uint16_t spd_addr [] = {
 100                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 101                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 102 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 103                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 104                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 105 #endif
 106         };
 107
 108         int needs_reset;
 109         unsigned bsp_apicid = 0;
 110
 111         struct mem_controller ctrl[8];
 112         unsigned nodes;
 113
 114         if (!cpu_init_detectedx && boot_cpu()) {
 115                 /* Nothing special needs to be done to find bus 0 */
 116                 /* Allow the HT devices to be found */
 117
 118                 enumerate_ht_chain();
 119
 120                 sio_setup();
 121         }
 122
 123         if (bist == 0) {
 124                 bsp_apicid = init_cpus(cpu_init_detectedx);
 125         }
 126
 127 //      post_code(0x32);
 128
 129         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 130         uart_init();
 131         console_init();
 132
 133         /* Halt if there was a built in self test failure */
 134         report_bist_failure(bist);
 135
 136         setup_s2891_resource_map();
 137 #if 0
 138         dump_pci_device(PCI_DEV(0, 0x18, 0));
 139         dump_pci_device(PCI_DEV(0, 0x19, 0));
 140 #endif
 141
 142         needs_reset = setup_coherent_ht_domain();
 143
 144         wait_all_core0_started();
 145 #if CONFIG_LOGICAL_CPUS==1
 146         // It is said that we should start core1 after all core0 launched
 147         start_other_cores();
 148         wait_all_other_cores_started(bsp_apicid);
 149 #endif
 150
 151         needs_reset |= ht_setup_chains_x();
 152
 153         needs_reset |= ck804_early_setup_x();
 154
 155         if (needs_reset) {
 156                 printk(BIOS_INFO, "ht reset -\n");
 157                 soft_reset();
 158         }
 159
 160         allow_all_aps_stop(bsp_apicid);
 161
 162         nodes = get_nodes();
 163         //It's the time to set ctrl now;
 164         fill_mem_ctrl(nodes, ctrl, spd_addr);
 165
 166         enable_smbus();
 167 #if 0
 168         dump_spd_registers(&cpu[0]);
 169 #endif
 170 #if 0
 171         dump_smbus_registers();
 172 #endif
 173
 174         memreset_setup();
 175         sdram_initialize(nodes, ctrl);
 176
 177 #if 0
 178         print_pci_devices();
 179 #endif
 180
 181 #if 0
 182         dump_pci_devices();
 183 #endif
 184
 185         post_cache_as_ram();
 186 }
 187