src/mainboard/tyan/s2891/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12
  13 #include <cpu/amd/model_fxx_rev.h>
  14
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29
  30 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  31
  32 static void memreset_setup(void)
  33 {
  34 }
  35
  36 static void memreset(int controllers, const struct mem_controller *ctrl)
  37 {
  38 }
  39
  40 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  41 {
  42         /* nothing to do */
  43 }
  44
  45 static inline int spd_read_byte(unsigned device, unsigned address)
  46 {
  47         return smbus_read_byte(device, address);
  48 }
  49
  50 #include "northbridge/amd/amdk8/raminit.c"
  51 #include "northbridge/amd/amdk8/coherent_ht.c"
  52 #include "lib/generic_sdram.c"
  53
  54  /* tyan does not want the default */
  55 #include "resourcemap.c"
  56
  57 #include "cpu/amd/dualcore/dualcore.c"
  58
  59 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  60 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  61
  62 #include "cpu/amd/car/post_cache_as_ram.c"
  63
  64 #include "cpu/amd/model_fxx/init_cpus.c"
  65
  66 #include "northbridge/amd/amdk8/early_ht.c"
  67
  68 static void sio_setup(void)
  69 {
  70         uint32_t dword;
  71         uint8_t byte;
  72
  73         /* subject decoding*/
  74         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  75         byte |= 0x20;
  76         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  77
  78         /* LPC Positive Decode 0 */
  79         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  80         /* Serial 0, Serial 1 */
  81         dword |= (1<<0) | (1<<1);
  82         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  83
  84 #if 1
  85         /* s2891 has onboard LPC port 80 */
  86         /*Hope I can enable port 80 here
  87         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
  88         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
  89         dword |= (1<<16);
  90         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
  91 #endif
  92 }
  93
  94 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  95 {
  96         static const uint16_t spd_addr [] = {
  97                 DIMM0, DIMM2, 0, 0,
  98                 DIMM1, DIMM3, 0, 0,
  99 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 100                 DIMM4, DIMM6, 0, 0,
 101                 DIMM5, DIMM7, 0, 0,
 102 #endif
 103         };
 104
 105         int needs_reset;
 106         unsigned bsp_apicid = 0;
 107
 108         struct mem_controller ctrl[8];
 109         unsigned nodes;
 110
 111         if (!cpu_init_detectedx && boot_cpu()) {
 112                 /* Nothing special needs to be done to find bus 0 */
 113                 /* Allow the HT devices to be found */
 114
 115                 enumerate_ht_chain();
 116
 117                 sio_setup();
 118         }
 119
 120         if (bist == 0) {
 121                 bsp_apicid = init_cpus(cpu_init_detectedx);
 122         }
 123
 124 //      post_code(0x32);
 125
 126         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 127         uart_init();
 128         console_init();
 129
 130         /* Halt if there was a built in self test failure */
 131         report_bist_failure(bist);
 132
 133         setup_s2891_resource_map();
 134 #if 0
 135         dump_pci_device(PCI_DEV(0, 0x18, 0));
 136         dump_pci_device(PCI_DEV(0, 0x19, 0));
 137 #endif
 138
 139         needs_reset = setup_coherent_ht_domain();
 140
 141         wait_all_core0_started();
 142 #if CONFIG_LOGICAL_CPUS==1
 143         // It is said that we should start core1 after all core0 launched
 144         start_other_cores();
 145         wait_all_other_cores_started(bsp_apicid);
 146 #endif
 147
 148         needs_reset |= ht_setup_chains_x();
 149
 150         needs_reset |= ck804_early_setup_x();
 151
 152         if (needs_reset) {
 153                 printk(BIOS_INFO, "ht reset -\n");
 154                 soft_reset();
 155         }
 156
 157         allow_all_aps_stop(bsp_apicid);
 158
 159         nodes = get_nodes();
 160         //It's the time to set ctrl now;
 161         fill_mem_ctrl(nodes, ctrl, spd_addr);
 162
 163         enable_smbus();
 164 #if 0
 165         dump_spd_registers(&cpu[0]);
 166 #endif
 167 #if 0
 168         dump_smbus_registers();
 169 #endif
 170
 171         memreset_setup();
 172         sdram_initialize(nodes, ctrl);
 173
 174 #if 0
 175         print_pci_devices();
 176 #endif
 177
 178 #if 0
 179         dump_pci_devices();
 180 #endif
 181
 182         post_cache_as_ram();
 183 }
 184