src/mainboard/tyan/s2891/romstage.c

   1 //used by raminit
   2
   3 #if CONFIG_LOGICAL_CPUS==1
   4 #define SET_NB_CFG_54 1
   5 #endif
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include <pc80/mc146818rtc.h>
  15 #include <console/console.h>
  16 #include <lib.h>
  17
  18 #include <cpu/amd/model_fxx_rev.h>
  19
  20 #include "northbridge/amd/amdk8/incoherent_ht.c"
  21 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  22 #include "northbridge/amd/amdk8/raminit.h"
  23 #include "cpu/amd/model_fxx/apic_timer.c"
  24 #include "lib/delay.c"
  25 #include "cpu/x86/lapic/boot_cpu.c"
  26 #include "northbridge/amd/amdk8/reset_test.c"
  27 #include "northbridge/amd/amdk8/debug.c"
  28 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  29
  30 #include "cpu/x86/mtrr/earlymtrr.c"
  31 #include "cpu/x86/bist.h"
  32
  33 #include "northbridge/amd/amdk8/setup_resource_map.c"
  34
  35 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  36
  37 static void memreset_setup(void)
  38 {
  39 }
  40
  41 static void memreset(int controllers, const struct mem_controller *ctrl)
  42 {
  43 }
  44
  45 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  46 {
  47         /* nothing to do */
  48 }
  49
  50 static inline int spd_read_byte(unsigned device, unsigned address)
  51 {
  52         return smbus_read_byte(device, address);
  53 }
  54
  55 #include "northbridge/amd/amdk8/raminit.c"
  56 #include "northbridge/amd/amdk8/coherent_ht.c"
  57 #include "lib/generic_sdram.c"
  58
  59  /* tyan does not want the default */
  60 #include "resourcemap.c"
  61
  62 #include "cpu/amd/dualcore/dualcore.c"
  63
  64 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  65 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  66
  67 #include "cpu/amd/car/post_cache_as_ram.c"
  68
  69 #include "cpu/amd/model_fxx/init_cpus.c"
  70
  71 #include "northbridge/amd/amdk8/early_ht.c"
  72
  73 static void sio_setup(void)
  74 {
  75         uint32_t dword;
  76         uint8_t byte;
  77
  78         /* subject decoding*/
  79         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  80         byte |= 0x20;
  81         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  82
  83         /* LPC Positive Decode 0 */
  84         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  85         /* Serial 0, Serial 1 */
  86         dword |= (1<<0) | (1<<1);
  87         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  88
  89 #if 1
  90         /* s2891 has onboard LPC port 80 */
  91         /*Hope I can enable port 80 here
  92         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
  93         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
  94         dword |= (1<<16);
  95         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
  96 #endif
  97 }
  98
  99 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 100 {
 101         static const uint16_t spd_addr [] = {
 102                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 103                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 104 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 105                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 106                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 107 #endif
 108         };
 109
 110         int needs_reset;
 111         unsigned bsp_apicid = 0;
 112
 113         struct mem_controller ctrl[8];
 114         unsigned nodes;
 115
 116         if (!cpu_init_detectedx && boot_cpu()) {
 117                 /* Nothing special needs to be done to find bus 0 */
 118                 /* Allow the HT devices to be found */
 119
 120                 enumerate_ht_chain();
 121
 122                 sio_setup();
 123         }
 124
 125         if (bist == 0) {
 126                 bsp_apicid = init_cpus(cpu_init_detectedx);
 127         }
 128
 129 //      post_code(0x32);
 130
 131         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 132         uart_init();
 133         console_init();
 134
 135         /* Halt if there was a built in self test failure */
 136         report_bist_failure(bist);
 137
 138         setup_s2891_resource_map();
 139 #if 0
 140         dump_pci_device(PCI_DEV(0, 0x18, 0));
 141         dump_pci_device(PCI_DEV(0, 0x19, 0));
 142 #endif
 143
 144         needs_reset = setup_coherent_ht_domain();
 145
 146         wait_all_core0_started();
 147 #if CONFIG_LOGICAL_CPUS==1
 148         // It is said that we should start core1 after all core0 launched
 149         start_other_cores();
 150         wait_all_other_cores_started(bsp_apicid);
 151 #endif
 152
 153         needs_reset |= ht_setup_chains_x();
 154
 155         needs_reset |= ck804_early_setup_x();
 156
 157         if (needs_reset) {
 158                 printk(BIOS_INFO, "ht reset -\n");
 159                 soft_reset();
 160         }
 161
 162         allow_all_aps_stop(bsp_apicid);
 163
 164         nodes = get_nodes();
 165         //It's the time to set ctrl now;
 166         fill_mem_ctrl(nodes, ctrl, spd_addr);
 167
 168         enable_smbus();
 169 #if 0
 170         dump_spd_registers(&cpu[0]);
 171 #endif
 172 #if 0
 173         dump_smbus_registers();
 174 #endif
 175
 176         memreset_setup();
 177         sdram_initialize(nodes, ctrl);
 178
 179 #if 0
 180         print_pci_devices();
 181 #endif
 182
 183 #if 0
 184         dump_pci_devices();
 185 #endif
 186
 187         post_cache_as_ram();
 188 }
 189