src/mainboard/tyan/s2891/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  22 #include "cpu/x86/mtrr/earlymtrr.c"
  23 #include "cpu/x86/bist.h"
  24 #include "northbridge/amd/amdk8/setup_resource_map.c"
  25
  26 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  27
  28 static void memreset_setup(void)
  29 {
  30 }
  31
  32 static void memreset(int controllers, const struct mem_controller *ctrl)
  33 {
  34 }
  35
  36 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  37 {
  38         /* nothing to do */
  39 }
  40
  41 static inline int spd_read_byte(unsigned device, unsigned address)
  42 {
  43         return smbus_read_byte(device, address);
  44 }
  45
  46 #include "northbridge/amd/amdk8/raminit.c"
  47 #include "northbridge/amd/amdk8/coherent_ht.c"
  48 #include "lib/generic_sdram.c"
  49 #include "resourcemap.c" /* tyan does not want the default */
  50 #include "cpu/amd/dualcore/dualcore.c"
  51 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  52 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  53 #include "cpu/amd/car/post_cache_as_ram.c"
  54 #include "cpu/amd/model_fxx/init_cpus.c"
  55 #include "northbridge/amd/amdk8/early_ht.c"
  56
  57 static void sio_setup(void)
  58 {
  59         uint32_t dword;
  60         uint8_t byte;
  61
  62         /* subject decoding*/
  63         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  64         byte |= 0x20;
  65         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  66
  67         /* LPC Positive Decode 0 */
  68         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  69         /* Serial 0, Serial 1 */
  70         dword |= (1<<0) | (1<<1);
  71         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  72
  73 #if 1
  74         /* s2891 has onboard LPC port 80 */
  75         /*Hope I can enable port 80 here
  76         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
  77         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
  78         dword |= (1<<16);
  79         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
  80 #endif
  81 }
  82
  83 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  84 {
  85         static const uint16_t spd_addr [] = {
  86                 DIMM0, DIMM2, 0, 0,
  87                 DIMM1, DIMM3, 0, 0,
  88 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  89                 DIMM4, DIMM6, 0, 0,
  90                 DIMM5, DIMM7, 0, 0,
  91 #endif
  92         };
  93
  94         int needs_reset;
  95         unsigned bsp_apicid = 0;
  96
  97         struct mem_controller ctrl[8];
  98         unsigned nodes;
  99
 100         if (!cpu_init_detectedx && boot_cpu()) {
 101                 /* Nothing special needs to be done to find bus 0 */
 102                 /* Allow the HT devices to be found */
 103
 104                 enumerate_ht_chain();
 105
 106                 sio_setup();
 107         }
 108
 109         if (bist == 0) {
 110                 bsp_apicid = init_cpus(cpu_init_detectedx);
 111         }
 112
 113 //      post_code(0x32);
 114
 115         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 116         uart_init();
 117         console_init();
 118
 119         /* Halt if there was a built in self test failure */
 120         report_bist_failure(bist);
 121
 122         setup_s2891_resource_map();
 123 #if 0
 124         dump_pci_device(PCI_DEV(0, 0x18, 0));
 125         dump_pci_device(PCI_DEV(0, 0x19, 0));
 126 #endif
 127
 128         needs_reset = setup_coherent_ht_domain();
 129
 130         wait_all_core0_started();
 131 #if CONFIG_LOGICAL_CPUS==1
 132         // It is said that we should start core1 after all core0 launched
 133         start_other_cores();
 134         wait_all_other_cores_started(bsp_apicid);
 135 #endif
 136
 137         needs_reset |= ht_setup_chains_x();
 138
 139         needs_reset |= ck804_early_setup_x();
 140
 141         if (needs_reset) {
 142                 printk(BIOS_INFO, "ht reset -\n");
 143                 soft_reset();
 144         }
 145
 146         allow_all_aps_stop(bsp_apicid);
 147
 148         nodes = get_nodes();
 149         //It's the time to set ctrl now;
 150         fill_mem_ctrl(nodes, ctrl, spd_addr);
 151
 152         enable_smbus();
 153 #if 0
 154         dump_spd_registers(&cpu[0]);
 155 #endif
 156 #if 0
 157         dump_smbus_registers();
 158 #endif
 159
 160         memreset_setup();
 161         sdram_initialize(nodes, ctrl);
 162
 163 #if 0
 164         print_pci_devices();
 165 #endif
 166
 167 #if 0
 168         dump_pci_devices();
 169 #endif
 170
 171         post_cache_as_ram();
 172 }
 173