src/mainboard/tyan/s2891/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 //used by raminit
   5 #define QRANK_DIMM_SUPPORT 1
   6
   7 #if CONFIG_LOGICAL_CPUS==1
   8 #define SET_NB_CFG_54 1
   9 #endif
  10
  11 #include <stdint.h>
  12 #include <string.h>
  13 #include <device/pci_def.h>
  14 #include <arch/io.h>
  15 #include <device/pnp_def.h>
  16 #include <arch/romcc_io.h>
  17 #include <cpu/x86/lapic.h>
  18 #include "option_table.h"
  19 #include "pc80/mc146818rtc_early.c"
  20 #include "pc80/serial.c"
  21 #include "arch/i386/lib/console.c"
  22 #include "lib/ramtest.c"
  23
  24 #include <cpu/amd/model_fxx_rev.h>
  25
  26 #include "northbridge/amd/amdk8/incoherent_ht.c"
  27 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  28 #include "northbridge/amd/amdk8/raminit.h"
  29 #include "cpu/amd/model_fxx/apic_timer.c"
  30 #include "lib/delay.c"
  31 #include "cpu/x86/lapic/boot_cpu.c"
  32 #include "northbridge/amd/amdk8/reset_test.c"
  33 #include "northbridge/amd/amdk8/debug.c"
  34 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  35
  36 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  37 #include "cpu/x86/bist.h"
  38
  39 #include "northbridge/amd/amdk8/setup_resource_map.c"
  40
  41 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  42
  43 static void memreset_setup(void)
  44 {
  45 }
  46
  47 static void memreset(int controllers, const struct mem_controller *ctrl)
  48 {
  49 }
  50
  51 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  52 {
  53         /* nothing to do */
  54 }
  55
  56 static inline int spd_read_byte(unsigned device, unsigned address)
  57 {
  58         return smbus_read_byte(device, address);
  59 }
  60
  61 #include "northbridge/amd/amdk8/raminit.c"
  62 #include "northbridge/amd/amdk8/coherent_ht.c"
  63 #include "lib/generic_sdram.c"
  64
  65  /* tyan does not want the default */
  66 #include "resourcemap.c"
  67
  68 #include "cpu/amd/dualcore/dualcore.c"
  69
  70 #define CK804_NUM 1
  71 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  72 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  73
  74 #include "cpu/amd/car/copy_and_run.c"
  75
  76 #include "cpu/amd/car/post_cache_as_ram.c"
  77
  78 #include "cpu/amd/model_fxx/init_cpus.c"
  79
  80 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  81 #include "northbridge/amd/amdk8/early_ht.c"
  82
  83 static void sio_setup(void)
  84 {
  85
  86         unsigned value;
  87         uint32_t dword;
  88         uint8_t byte;
  89
  90         /* subject decoding*/
  91         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  92         byte |= 0x20;
  93         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  94
  95         /* LPC Positive Decode 0 */
  96         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  97         /* Serial 0, Serial 1 */
  98         dword |= (1<<0) | (1<<1);
  99         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 100
 101 #if 1
 102         /* s2891 has onboard LPC port 80 */
 103         /*Hope I can enable port 80 here
 104         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
 105         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
 106         dword |= (1<<16);
 107         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 108
 109 #endif
 110
 111 }
 112
 113 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 114 {
 115         static const uint16_t spd_addr [] = {
 116                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 117                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 118 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 119                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 120                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 121 #endif
 122         };
 123
 124         int needs_reset;
 125         unsigned bsp_apicid = 0;
 126
 127         struct mem_controller ctrl[8];
 128         unsigned nodes;
 129
 130         if (!cpu_init_detectedx && boot_cpu()) {
 131                 /* Nothing special needs to be done to find bus 0 */
 132                 /* Allow the HT devices to be found */
 133
 134                 enumerate_ht_chain();
 135
 136                 sio_setup();
 137
 138                 /* Setup the ck804 */
 139                 ck804_enable_rom();
 140         }
 141
 142         if (bist == 0) {
 143                 bsp_apicid = init_cpus(cpu_init_detectedx);
 144         }
 145
 146 //      post_code(0x32);
 147
 148         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 149         uart_init();
 150         console_init();
 151
 152         /* Halt if there was a built in self test failure */
 153         report_bist_failure(bist);
 154
 155         setup_s2891_resource_map();
 156 #if 0
 157         dump_pci_device(PCI_DEV(0, 0x18, 0));
 158         dump_pci_device(PCI_DEV(0, 0x19, 0));
 159 #endif
 160
 161         needs_reset = setup_coherent_ht_domain();
 162
 163         wait_all_core0_started();
 164 #if CONFIG_LOGICAL_CPUS==1
 165         // It is said that we should start core1 after all core0 launched
 166         start_other_cores();
 167         wait_all_other_cores_started(bsp_apicid);
 168 #endif
 169
 170         needs_reset |= ht_setup_chains_x();
 171
 172         needs_reset |= ck804_early_setup_x();
 173
 174         if (needs_reset) {
 175                 printk_info("ht reset -\r\n");
 176                 soft_reset();
 177         }
 178
 179         allow_all_aps_stop(bsp_apicid);
 180
 181         nodes = get_nodes();
 182         //It's the time to set ctrl now;
 183         fill_mem_ctrl(nodes, ctrl, spd_addr);
 184
 185         enable_smbus();
 186 #if 0
 187         dump_spd_registers(&cpu[0]);
 188 #endif
 189 #if 0
 190         dump_smbus_registers();
 191 #endif
 192
 193         memreset_setup();
 194         sdram_initialize(nodes, ctrl);
 195
 196 #if 0
 197         print_pci_devices();
 198 #endif
 199
 200 #if 0
 201         dump_pci_devices();
 202 #endif
 203
 204         post_cache_as_ram();
 205 }