src/mainboard/tyan/s2891/resourcemap.c

   1 /*
   2  * Tyan S2891 needs a different resource map
   3  *
   4  */
   5
   6 static void setup_s2891_resource_map(void)
   7 {
   8         static const unsigned int register_values[] = {
   9 #if 1
  10                 /* Careful set limit registers before base registers which contain the enables */
  11                 /* DRAM Limit i Registers
  12                  * F1:0x44 i = 0
  13                  * F1:0x4C i = 1
  14                  * F1:0x54 i = 2
  15                  * F1:0x5C i = 3
  16                  * F1:0x64 i = 4
  17                  * F1:0x6C i = 5
  18                  * F1:0x74 i = 6
  19                  * F1:0x7C i = 7
  20                  * [ 2: 0] Destination Node ID
  21                  *         000 = Node 0
  22                  *         001 = Node 1
  23                  *         010 = Node 2
  24                  *         011 = Node 3
  25                  *         100 = Node 4
  26                  *         101 = Node 5
  27                  *         110 = Node 6
  28                  *         111 = Node 7
  29                  * [ 7: 3] Reserved
  30                  * [10: 8] Interleave select
  31                  *         specifies the values of A[14:12] to use with interleave enable.
  32                  * [15:11] Reserved
  33                  * [31:16] DRAM Limit Address i Bits 39-24
  34                  *         This field defines the upper address bits of a 40 bit  address
  35                  *         that define the end of the DRAM region.
  36                  */
  37                 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
  38                 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
  39                 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
  40                 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
  41                 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
  42                 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
  43                 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
  44                 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
  45                 /* DRAM Base i Registers
  46                  * F1:0x40 i = 0
  47                  * F1:0x48 i = 1
  48                  * F1:0x50 i = 2
  49                  * F1:0x58 i = 3
  50                  * F1:0x60 i = 4
  51                  * F1:0x68 i = 5
  52                  * F1:0x70 i = 6
  53                  * F1:0x78 i = 7
  54                  * [ 0: 0] Read Enable
  55                  *         0 = Reads Disabled
  56                  *         1 = Reads Enabled
  57                  * [ 1: 1] Write Enable
  58                  *         0 = Writes Disabled
  59                  *         1 = Writes Enabled
  60                  * [ 7: 2] Reserved
  61                  * [10: 8] Interleave Enable
  62                  *         000 = No interleave
  63                  *         001 = Interleave on A[12] (2 nodes)
  64                  *         010 = reserved
  65                  *         011 = Interleave on A[12] and A[14] (4 nodes)
  66                  *         100 = reserved
  67                  *         101 = reserved
  68                  *         110 = reserved
  69                  *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
  70                  * [15:11] Reserved
  71                  * [13:16] DRAM Base Address i Bits 39-24
  72                  *         This field defines the upper address bits of a 40-bit address
  73                  *         that define the start of the DRAM region.
  74                  */
  75                 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
  76                 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
  77                 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
  78                 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
  79                 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
  80                 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
  81                 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
  82                 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
  83 #endif
  84 #if 1
  85
  86                 /* Memory-Mapped I/O Limit i Registers
  87                  * F1:0x84 i = 0
  88                  * F1:0x8C i = 1
  89                  * F1:0x94 i = 2
  90                  * F1:0x9C i = 3
  91                  * F1:0xA4 i = 4
  92                  * F1:0xAC i = 5
  93                  * F1:0xB4 i = 6
  94                  * F1:0xBC i = 7
  95                  * [ 2: 0] Destination Node ID
  96                  *         000 = Node 0
  97                  *         001 = Node 1
  98                  *         010 = Node 2
  99                  *         011 = Node 3
 100                  *         100 = Node 4
 101                  *         101 = Node 5
 102                  *         110 = Node 6
 103                  *         111 = Node 7
 104                  * [ 3: 3] Reserved
 105                  * [ 5: 4] Destination Link ID
 106                  *         00 = Link 0
 107                  *         01 = Link 1
 108                  *         10 = Link 2
 109                  *         11 = Reserved
 110                  * [ 6: 6] Reserved
 111                  * [ 7: 7] Non-Posted
 112                  *         0 = CPU writes may be posted
 113                  *         1 = CPU writes must be non-posted
 114                  * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
 115                  *         This field defines the upp adddress bits of a 40-bit address that
 116                  *         defines the end of a memory-mapped I/O region n
 117                  */
 118                 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
 119                 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
 120                 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
 121                 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
 122                 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
 123                 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
 124                 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
 125 //              PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
 126
 127                 /* Memory-Mapped I/O Base i Registers
 128                  * F1:0x80 i = 0
 129                  * F1:0x88 i = 1
 130                  * F1:0x90 i = 2
 131                  * F1:0x98 i = 3
 132                  * F1:0xA0 i = 4
 133                  * F1:0xA8 i = 5
 134                  * F1:0xB0 i = 6
 135                  * F1:0xB8 i = 7
 136                  * [ 0: 0] Read Enable
 137                  *         0 = Reads disabled
 138                  *         1 = Reads Enabled
 139                  * [ 1: 1] Write Enable
 140                  *         0 = Writes disabled
 141                  *         1 = Writes Enabled
 142                  * [ 2: 2] Cpu Disable
 143                  *         0 = Cpu can use this I/O range
 144                  *         1 = Cpu requests do not use this I/O range
 145                  * [ 3: 3] Lock
 146                  *         0 = base/limit registers i are read/write
 147                  *         1 = base/limit registers i are read-only
 148                  * [ 7: 4] Reserved
 149                  * [31: 8] Memory-Mapped I/O Base Address i (39-16)
 150                  *         This field defines the upper address bits of a 40bit address
 151                  *         that defines the start of memory-mapped I/O region i
 152                  */
 153                 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
 154                 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
 155                 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
 156                 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
 157                 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
 158                 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
 159                 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
 160 //              PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
 161 #endif
 162 #if 1
 163
 164                 /* PCI I/O Limit i Registers
 165                  * F1:0xC4 i = 0
 166                  * F1:0xCC i = 1
 167                  * F1:0xD4 i = 2
 168                  * F1:0xDC i = 3
 169                  * [ 2: 0] Destination Node ID
 170                  *         000 = Node 0
 171                  *         001 = Node 1
 172                  *         010 = Node 2
 173                  *         011 = Node 3
 174                  *         100 = Node 4
 175                  *         101 = Node 5
 176                  *         110 = Node 6
 177                  *         111 = Node 7
 178                  * [ 3: 3] Reserved
 179                  * [ 5: 4] Destination Link ID
 180                  *         00 = Link 0
 181                  *         01 = Link 1
 182                  *         10 = Link 2
 183                  *         11 = reserved
 184                  * [11: 6] Reserved
 185                  * [24:12] PCI I/O Limit Address i
 186                  *         This field defines the end of PCI I/O region n
 187                  * [31:25] Reserved
 188                  */
 189                 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
 190                 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
 191                 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 192                 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 193
 194                 /* PCI I/O Base i Registers
 195                  * F1:0xC0 i = 0
 196                  * F1:0xC8 i = 1
 197                  * F1:0xD0 i = 2
 198                  * F1:0xD8 i = 3
 199                  * [ 0: 0] Read Enable
 200                  *         0 = Reads Disabled
 201                  *         1 = Reads Enabled
 202                  * [ 1: 1] Write Enable
 203                  *         0 = Writes Disabled
 204                  *         1 = Writes Enabled
 205                  * [ 3: 2] Reserved
 206                  * [ 4: 4] VGA Enable
 207                  *         0 = VGA matches Disabled
 208                  *         1 = matches all address < 64K and where A[9:0] is in the
 209                  *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 210                  * [ 5: 5] ISA Enable
 211                  *         0 = ISA matches Disabled
 212                  *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
 213                  *             from matching agains this base/limit pair
 214                  * [11: 6] Reserved
 215                  * [24:12] PCI I/O Base i
 216                  *         This field defines the start of PCI I/O region n
 217                  * [31:25] Reserved
 218                  */
 219                 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
 220                 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
 221                 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 222                 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
 223 #endif
 224                 /* Config Base and Limit i Registers
 225                  * F1:0xE0 i = 0
 226                  * F1:0xE4 i = 1
 227                  * F1:0xE8 i = 2
 228                  * F1:0xEC i = 3
 229                  * [ 0: 0] Read Enable
 230                  *         0 = Reads Disabled
 231                  *         1 = Reads Enabled
 232                  * [ 1: 1] Write Enable
 233                  *         0 = Writes Disabled
 234                  *         1 = Writes Enabled
 235                  * [ 2: 2] Device Number Compare Enable
 236                  *         0 = The ranges are based on bus number
 237                  *         1 = The ranges are ranges of devices on bus 0
 238                  * [ 3: 3] Reserved
 239                  * [ 6: 4] Destination Node
 240                  *         000 = Node 0
 241                  *         001 = Node 1
 242                  *         010 = Node 2
 243                  *         011 = Node 3
 244                  *         100 = Node 4
 245                  *         101 = Node 5
 246                  *         110 = Node 6
 247                  *         111 = Node 7
 248                  * [ 7: 7] Reserved
 249                  * [ 9: 8] Destination Link
 250                  *         00 = Link 0
 251                  *         01 = Link 1
 252                  *         10 = Link 2
 253                  *         11 - Reserved
 254                  * [15:10] Reserved
 255                  * [23:16] Bus Number Base i
 256                  *         This field defines the lowest bus number in configuration region i
 257                  * [31:24] Bus Number Limit i
 258                  *         This field defines the highest bus number in configuration region i
 259                  */
 260 #if 1
 261 //              PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
 262 //              PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
 263                 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 264                 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 265 #endif
 266
 267         };
 268
 269         int max;
 270         max = sizeof(register_values)/sizeof(register_values[0]);
 271         setup_resource_map(register_values, max);
 272 }
 273