1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #include <cpu/amd/amdk8_sysconf.h>
8 extern unsigned char bus_ck804_0; //1
9 extern unsigned char bus_ck804_1; //2
10 extern unsigned char bus_ck804_2; //3
11 extern unsigned char bus_ck804_3; //4
12 extern unsigned char bus_ck804_4; //5
13 extern unsigned char bus_ck804_5; //6
14 extern unsigned char bus_8131_0; //7
15 extern unsigned char bus_8131_1; //8
16 extern unsigned char bus_8131_2; //9
17 extern unsigned apicid_ck804;
18 extern unsigned apicid_8131_1;
19 extern unsigned apicid_8131_2;
21 extern unsigned sbdn3;
23 static void *smp_write_config_table(void *v)
25 struct mp_config_table *mc;
29 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
31 mptable_init(mc, LOCAL_APIC_ADDR);
33 smp_write_processors(mc);
38 mptable_write_buses(mc, NULL, &bus_isa);
40 /*I/O APICs: APIC ID Version State Address*/
46 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
48 res = find_resource(dev, PCI_BASE_ADDRESS_1);
50 smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
53 /* Initialize interrupt mapping*/
56 pci_write_config32(dev, 0x7c, dword);
59 pci_write_config32(dev, 0x80, dword);
62 pci_write_config32(dev, 0x84, dword);
66 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
68 res = find_resource(dev, PCI_BASE_ADDRESS_0);
70 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
73 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
75 res = find_resource(dev, PCI_BASE_ADDRESS_0);
77 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
83 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
85 // Onboard ck804 smbus
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
88 // Onboard ck804 USB 1.1
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
91 // Onboard ck804 USB 2
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
94 // Onboard ck804 SATA 0
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
97 // Onboard ck804 SATA 1
98 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19
116 //Onboard Broadcom NIC
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
123 //Slot 4 PCIX 133/100/66
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24
128 //Slot 3 PCIX 133/100/66 SoDIMM PCI
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26
133 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
134 mptable_lintsrc(mc, bus_isa);
135 /* There is no extension information... */
137 /* Compute the checksums */
138 return mptable_finalize(mc);
141 unsigned long write_smp_table(unsigned long addr)
144 v = smp_write_floating_table(addr, 0);
145 return (unsigned long)smp_write_config_table(v);