4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
31 uses LB_CKS_RANGE_START
35 uses HAVE_MAINBOARD_RESOURCES
41 uses MAINBOARD_PART_NUMBER
43 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
44 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
45 uses COREBOOT_EXTRA_VERSION
55 uses DEFAULT_CONSOLE_LOGLEVEL
56 uses MAXIMUM_CONSOLE_LOGLEVEL
57 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
58 uses CONFIG_CONSOLE_SERIAL8250
59 uses CONFIG_CONSOLE_BTEXT
62 uses CONFIG_CONSOLE_VGA
63 uses CONFIG_VGA_ROM_RUN
64 uses CONFIG_PCI_ROM_RUN
65 uses HW_MEM_HOLE_SIZEK
71 uses CONFIG_USE_PRINTK_IN_CAR
73 uses ENABLE_APIC_EXT_ID
77 uses CONFIG_PCI_64BIT_PREF_MEM
79 uses HT_CHAIN_UNITID_BASE
80 uses HT_CHAIN_END_UNITID_BASE
81 uses SB_HT_CHAIN_ON_BUS0
82 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
84 uses CONFIG_LB_MEM_TOPK
86 ## ROM_SIZE is the size of boot ROM that this board will use.
87 default ROM_SIZE=512*1024
90 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
92 #default FALLBACK_SIZE=131072
94 default FALLBACK_SIZE=0x40000
101 ## Build code for the fallback boot
103 default HAVE_FALLBACK_BOOT=1
106 ## Build code to reset the motherboard from coreboot
108 default HAVE_HARD_RESET=1
113 default HAVE_SMI_HANDLER=0
116 ## Build code to export a programmable irq routing table
118 default HAVE_PIRQ_TABLE=1
119 default IRQ_SLOT_COUNT=11
122 ## Build code to export an x86 MP table
123 ## Useful for specifying IRQ routing values
125 default HAVE_MP_TABLE=1
128 ## Build code to provide ACPI support
130 default HAVE_ACPI_TABLES=1
131 default HAVE_LOW_TABLES=1
132 default HAVE_MAINBOARD_RESOURCES=1
133 default HAVE_HIGH_TABLES=0
134 default CONFIG_MULTIBOOT=0
137 ## Build code to export a CMOS option table
139 default HAVE_OPTION_TABLE=1
142 ## Move the default coreboot cmos range off of AMD RTC registers
144 default LB_CKS_RANGE_START=49
145 default LB_CKS_RANGE_END=122
146 default LB_CKS_LOC=123
149 default CONFIG_CONSOLE_VGA=1
150 default CONFIG_PCI_ROM_RUN=1
151 default CONFIG_VGA_ROM_RUN=1
154 ## Build code for SMP support
155 ## Only worry about 2 micro processors
158 default CONFIG_MAX_CPUS=4
159 default CONFIG_MAX_PHYSICAL_CPUS=2
160 default CONFIG_LOGICAL_CPUS=1
163 default HW_MEM_HOLE_SIZEK=0x100000
165 ##HT Unit ID offset, default is 1, the typical one
166 default HT_CHAIN_UNITID_BASE=0x0
168 ##real SB Unit ID, default is 0x20, mean dont touch it at last
169 #default HT_CHAIN_END_UNITID_BASE=0x0
171 #make the SB HT chain on bus 0, default is not (0)
172 default SB_HT_CHAIN_ON_BUS0=2
174 ##only offset for SB chain?, default is yes(1)
175 #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
178 #default CONFIG_CONSOLE_BTEXT=1
181 default CONFIG_CONSOLE_VGA=1
182 default CONFIG_PCI_ROM_RUN=1
185 ## enable CACHE_AS_RAM specifics
187 default USE_DCACHE_RAM=1
188 default DCACHE_RAM_BASE=0xcf000
189 default DCACHE_RAM_SIZE=0x1000
190 default CONFIG_USE_INIT=0
192 default ENABLE_APIC_EXT_ID=0
193 default APIC_ID_OFFSET=0x10
194 default LIFT_BSP_APIC_ID=0
197 #default CONFIG_PCI_64BIT_PREF_MEM=1
200 ## Build code to setup a generic IOAPIC
202 default CONFIG_IOAPIC=1
205 ## Clean up the motherboard id strings
207 default MAINBOARD_PART_NUMBER="s2891"
208 default MAINBOARD_VENDOR="Tyan"
209 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
210 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
213 ### coreboot layout values
216 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
217 default ROM_IMAGE_SIZE = 65536
220 ## Use a small 8K stack
222 default STACK_SIZE=0x2000
225 ## Use a small 16K heap
227 default HEAP_SIZE=0x4000
230 ## Only use the option table in a normal image
232 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
235 ## Coreboot C code runs at this location in RAM
237 default _RAMBASE=0x00004000
240 ## Load the payload from the ROM
242 default CONFIG_ROM_PAYLOAD = 1
245 ### Defaults of options that you may want to override in the target config file
249 ## The default compiler
251 default CC="$(CROSS_COMPILE)gcc -m32"
255 ## Disable the gdb stub by default
257 default CONFIG_GDB_STUB=0
259 default CONFIG_USE_PRINTK_IN_CAR=1
262 ## The Serial Console
265 # To Enable the Serial Console
266 default CONFIG_CONSOLE_SERIAL8250=1
268 ## Select the serial console baud rate
269 default TTYS0_BAUD=115200
270 #default TTYS0_BAUD=57600
271 #default TTYS0_BAUD=38400
272 #default TTYS0_BAUD=19200
273 #default TTYS0_BAUD=9600
274 #default TTYS0_BAUD=4800
275 #default TTYS0_BAUD=2400
276 #default TTYS0_BAUD=1200
278 # Select the serial console base port
279 default TTYS0_BASE=0x3f8
281 # Select the serial protocol
282 # This defaults to 8 data bits, 1 stop bit, and no parity
283 default TTYS0_LCS=0x3
286 ### Select the coreboot loglevel
288 ## EMERG 1 system is unusable
289 ## ALERT 2 action must be taken immediately
290 ## CRIT 3 critical conditions
291 ## ERR 4 error conditions
292 ## WARNING 5 warning conditions
293 ## NOTICE 6 normal but significant condition
294 ## INFO 7 informational
295 ## DEBUG 8 debug-level messages
296 ## SPEW 9 Way too many details
298 ## Request this level of debugging output
299 default DEFAULT_CONSOLE_LOGLEVEL=8
300 ## At a maximum only compile in this level of debugging
301 default MAXIMUM_CONSOLE_LOGLEVEL=8
304 ## Select power on after power fail setting
305 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
312 default CONFIG_ROMFS=0