4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
31 uses LB_CKS_RANGE_START
36 uses HAVE_MAINBOARD_RESOURCES
42 uses MAINBOARD_PART_NUMBER
44 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
45 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
46 uses COREBOOT_EXTRA_VERSION
56 uses DEFAULT_CONSOLE_LOGLEVEL
57 uses MAXIMUM_CONSOLE_LOGLEVEL
58 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
59 uses CONFIG_CONSOLE_SERIAL8250
60 uses CONFIG_CONSOLE_BTEXT
63 uses CONFIG_CONSOLE_VGA
64 uses CONFIG_VGA_ROM_RUN
65 uses CONFIG_PCI_ROM_RUN
66 uses HW_MEM_HOLE_SIZEK
72 uses CONFIG_USE_PRINTK_IN_CAR
74 uses ENABLE_APIC_EXT_ID
78 uses CONFIG_PCI_64BIT_PREF_MEM
80 uses HT_CHAIN_UNITID_BASE
81 uses HT_CHAIN_END_UNITID_BASE
82 uses SB_HT_CHAIN_ON_BUS0
83 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
85 uses CONFIG_LB_MEM_TOPK
87 ## ROM_SIZE is the size of boot ROM that this board will use.
88 default ROM_SIZE=512*1024
91 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
93 #default FALLBACK_SIZE=131072
95 default FALLBACK_SIZE=0x40000
102 ## Build code for the fallback boot
104 default HAVE_FALLBACK_BOOT=1
107 ## Build code to reset the motherboard from coreboot
109 default HAVE_HARD_RESET=1
114 default HAVE_SMI_HANDLER=0
117 ## Build code to export a programmable irq routing table
119 default HAVE_PIRQ_TABLE=1
120 default IRQ_SLOT_COUNT=11
123 ## Build code to export an x86 MP table
124 ## Useful for specifying IRQ routing values
126 default HAVE_MP_TABLE=1
129 ## Build code to provide ACPI support
131 default HAVE_ACPI_TABLES=1
132 default HAVE_LOW_TABLES=1
133 default HAVE_MAINBOARD_RESOURCES=1
134 default HAVE_HIGH_TABLES=0
135 default CONFIG_MULTIBOOT=0
138 ## Build code to export a CMOS option table
140 default HAVE_OPTION_TABLE=1
143 ## Move the default coreboot cmos range off of AMD RTC registers
145 default LB_CKS_RANGE_START=49
146 default LB_CKS_RANGE_END=122
147 default LB_CKS_LOC=123
150 default CONFIG_CONSOLE_VGA=1
151 default CONFIG_PCI_ROM_RUN=1
152 default CONFIG_VGA_ROM_RUN=1
155 ## Build code for SMP support
156 ## Only worry about 2 micro processors
159 default CONFIG_MAX_CPUS=4
160 default CONFIG_MAX_PHYSICAL_CPUS=2
161 default CONFIG_LOGICAL_CPUS=1
164 default HW_MEM_HOLE_SIZEK=0x100000
166 ##HT Unit ID offset, default is 1, the typical one
167 default HT_CHAIN_UNITID_BASE=0x0
169 ##real SB Unit ID, default is 0x20, mean dont touch it at last
170 #default HT_CHAIN_END_UNITID_BASE=0x0
172 #make the SB HT chain on bus 0, default is not (0)
173 default SB_HT_CHAIN_ON_BUS0=2
175 ##only offset for SB chain?, default is yes(1)
176 #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
179 #default CONFIG_CONSOLE_BTEXT=1
182 default CONFIG_CONSOLE_VGA=1
183 default CONFIG_PCI_ROM_RUN=1
186 ## enable CACHE_AS_RAM specifics
188 default USE_DCACHE_RAM=1
189 default DCACHE_RAM_BASE=0xcf000
190 default DCACHE_RAM_SIZE=0x1000
191 default CONFIG_USE_INIT=0
193 default ENABLE_APIC_EXT_ID=0
194 default APIC_ID_OFFSET=0x10
195 default LIFT_BSP_APIC_ID=0
198 #default CONFIG_PCI_64BIT_PREF_MEM=1
201 ## Build code to setup a generic IOAPIC
203 default CONFIG_IOAPIC=1
206 ## Clean up the motherboard id strings
208 default MAINBOARD_PART_NUMBER="s2891"
209 default MAINBOARD_VENDOR="Tyan"
210 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
211 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
214 ### coreboot layout values
217 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
218 default ROM_IMAGE_SIZE = 65536
221 ## Use a small 8K stack
223 default STACK_SIZE=0x2000
226 ## Use a small 16K heap
228 default HEAP_SIZE=0x4000
231 ## Only use the option table in a normal image
233 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
236 ## Coreboot C code runs at this location in RAM
238 default _RAMBASE=0x00004000
241 ## Load the payload from the ROM
243 default CONFIG_ROM_PAYLOAD = 1
246 ### Defaults of options that you may want to override in the target config file
250 ## The default compiler
252 default CC="$(CROSS_COMPILE)gcc -m32"
256 ## Disable the gdb stub by default
258 default CONFIG_GDB_STUB=0
260 default CONFIG_USE_PRINTK_IN_CAR=1
263 ## The Serial Console
266 # To Enable the Serial Console
267 default CONFIG_CONSOLE_SERIAL8250=1
269 ## Select the serial console baud rate
270 default TTYS0_BAUD=115200
271 #default TTYS0_BAUD=57600
272 #default TTYS0_BAUD=38400
273 #default TTYS0_BAUD=19200
274 #default TTYS0_BAUD=9600
275 #default TTYS0_BAUD=4800
276 #default TTYS0_BAUD=2400
277 #default TTYS0_BAUD=1200
279 # Select the serial console base port
280 default TTYS0_BASE=0x3f8
282 # Select the serial protocol
283 # This defaults to 8 data bits, 1 stop bit, and no parity
284 default TTYS0_LCS=0x3
287 ### Select the coreboot loglevel
289 ## EMERG 1 system is unusable
290 ## ALERT 2 action must be taken immediately
291 ## CRIT 3 critical conditions
292 ## ERR 4 error conditions
293 ## WARNING 5 warning conditions
294 ## NOTICE 6 normal but significant condition
295 ## INFO 7 informational
296 ## DEBUG 8 debug-level messages
297 ## SPEW 9 Way too many details
299 ## Request this level of debugging output
300 default DEFAULT_CONSOLE_LOGLEVEL=8
301 ## At a maximum only compile in this level of debugging
302 default MAXIMUM_CONSOLE_LOGLEVEL=8
305 ## Select power on after power fail setting
306 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
313 default CONFIG_ROMFS=0