src/mainboard/tyan/s2891/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19 default CONFIG_ROM_STREAM     = 1
  20
  21 ##
  22 ## Compute where this copy of linuxBIOS will start in the boot rom
  23 ##
  24 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  25
  26 ##
  27 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  28 ## execution speed.
  29 ##
  30 ## XIP_ROM_SIZE must be a power of 2.
  31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  32 ##
  33 default XIP_ROM_SIZE=65536
  34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  35
  36 arch i386 end
  37
  38
  39 ##
  40 ## Build the objects we have code for in this directory.
  41 ##
  42
  43 driver mainboard.o
  44
  45 #dir /drivers/ati/ragexl
  46
  47 #needed by irq_tables and mptable and acpi_tables
  48 object get_bus_conf.o
  49
  50 if HAVE_MP_TABLE object mptable.o end
  51 if HAVE_PIRQ_TABLE object irq_tables.o end
  52 #object reset.o
  53
  54 if USE_DCACHE_RAM
  55
  56         if CONFIG_USE_INIT
  57
  58                 makerule ./auto.o
  59                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  60                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  61                 end
  62
  63         else
  64
  65                 makerule ./auto.inc
  66                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  67                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  68                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  69                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  70                 end
  71
  72         end
  73 else
  74
  75         ##
  76         ## Romcc output
  77         ##
  78         makerule ./failover.E
  79                 depends "$(MAINBOARD)/failover.c ./romcc"
  80                 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  81         end
  82
  83         makerule ./failover.inc
  84                 depends "$(MAINBOARD)/failover.c ./romcc"
  85                 action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  86         end
  87
  88         makerule ./auto.E
  89                 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  90                 action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  91         end
  92
  93         makerule ./auto.inc
  94                 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  95                 action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  96         end
  97
  98 end
  99
 100 ##
 101 ## Build our 16 bit and 32 bit linuxBIOS entry code
 102 ##
 103 if USE_FALLBACK_IMAGE
 104         mainboardinit cpu/x86/16bit/entry16.inc
 105         ldscript /cpu/x86/16bit/entry16.lds
 106 end
 107
 108 mainboardinit cpu/x86/32bit/entry32.inc
 109
 110
 111 if USE_DCACHE_RAM
 112         if CONFIG_USE_INIT
 113                 ldscript /cpu/x86/32bit/entry32.lds
 114         end
 115
 116         if CONFIG_USE_INIT
 117                 ldscript /cpu/amd/car/cache_as_ram.lds
 118         end
 119 end
 120
 121 ##
 122 ## Build our reset vector (This is where linuxBIOS is entered)
 123 ##
 124 if USE_FALLBACK_IMAGE
 125         mainboardinit cpu/x86/16bit/reset16.inc
 126         ldscript /cpu/x86/16bit/reset16.lds
 127 else
 128         mainboardinit cpu/x86/32bit/reset32.inc
 129         ldscript /cpu/x86/32bit/reset32.lds
 130 end
 131
 132 if USE_DCACHE_RAM
 133 else
 134         ### Should this be in the northbridge code?
 135         mainboardinit arch/i386/lib/cpu_reset.inc
 136 end
 137
 138 ##
 139 ## Include an id string (For safe flashing)
 140 ##
 141 mainboardinit southbridge/nvidia/ck804/id.inc
 142 ldscript /southbridge/nvidia/ck804/id.lds
 143
 144 ##
 145 ## ROMSTRAP table for CK804
 146 ##
 147 if USE_FALLBACK_IMAGE
 148         mainboardinit southbridge/nvidia/ck804/romstrap.inc
 149         ldscript /southbridge/nvidia/ck804/romstrap.lds
 150 end
 151
 152 if USE_DCACHE_RAM
 153         ##
 154         ## Setup Cache-As-Ram
 155         ##
 156         mainboardinit cpu/amd/car/cache_as_ram.inc
 157 end
 158
 159 ###
 160 ### This is the early phase of linuxBIOS startup
 161 ### Things are delicate and we test to see if we should
 162 ### failover to another image.
 163 ###
 164 if USE_FALLBACK_IMAGE
 165         ldscript /arch/i386/lib/failover.lds
 166         if USE_DCACHE_RAM
 167         else
 168                 mainboardinit ./failover.inc
 169         end
 170 end
 171
 172 ###
 173 ### O.k. We aren't just an intermediary anymore!
 174 ###
 175
 176 ##
 177 ## Setup RAM
 178 ##
 179 if USE_DCACHE_RAM
 180
 181         if CONFIG_USE_INIT
 182                 initobject auto.o
 183         else
 184                 mainboardinit ./auto.inc
 185         end
 186
 187 else
 188         # ROMCC
 189         mainboardinit cpu/x86/fpu/enable_fpu.inc
 190         mainboardinit cpu/x86/mmx/enable_mmx.inc
 191         mainboardinit cpu/x86/sse/enable_sse.inc
 192         mainboardinit ./auto.inc
 193         mainboardinit cpu/x86/sse/disable_sse.inc
 194         mainboardinit cpu/x86/mmx/disable_mmx.inc
 195
 196 end
 197
 198
 199 ##
 200 ## Include the secondary Configuration files
 201 ##
 202 if CONFIG_CHIP_NAME
 203         config chip.h
 204 end
 205
 206
 207 # sample config for tyan/s2891
 208 chip northbridge/amd/amdk8/root_complex
 209         device apic_cluster 0 on
 210                 chip cpu/amd/socket_940
 211                         device apic 0 on end
 212                 end
 213         end
 214
 215         device pci_domain 0 on
 216                 chip northbridge/amd/amdk8 #mc0
 217                         device pci 18.0 on #  northbridge
 218                                 #  devices on link 0, link 0 == LDT 0
 219                                 chip southbridge/nvidia/ck804
 220                                         device pci 0.0 on end   # HT
 221                                         device pci 1.0 on # LPC
 222                                                 chip superio/winbond/w83627hf
 223                                                         device pnp 2e.0 off #  Floppy
 224                                                                 io 0x60 = 0x3f0
 225                                                                 irq 0x70 = 6
 226                                                                 drq 0x74 = 2
 227                                                         end
 228                                                         device pnp 2e.1 off #  Parallel Port
 229                                                                 io 0x60 = 0x378
 230                                                                 irq 0x70 = 7
 231                                                         end
 232                                                         device pnp 2e.2 on #  Com1
 233                                                                 io 0x60 = 0x3f8
 234                                                                 irq 0x70 = 4
 235                                                         end
 236                                                         device pnp 2e.3 off #  Com2
 237                                                                 io 0x60 = 0x2f8
 238                                                                 irq 0x70 = 3
 239                                                         end
 240                                                         device pnp 2e.5 on #  Keyboard
 241                                                                 io 0x60 = 0x60
 242                                                                 io 0x62 = 0x64
 243                                                                 irq 0x70 = 1
 244                                                                 irq 0x72 = 12
 245                                                         end
 246                                                         device pnp 2e.6 off #  CIR
 247                                                                 io 0x60 = 0x100
 248                                                         end
 249                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 250                                                                 io 0x60 = 0x220
 251                                                                 io 0x62 = 0x300
 252                                                                 irq 0x70 = 9
 253                                                         end
 254                                                         device pnp 2e.8 off end #  GPIO2
 255                                                         device pnp 2e.9 off end #  GPIO3
 256                                                         device pnp 2e.a off end #  ACPI
 257                                                         device pnp 2e.b off #  HW Monitor
 258                                                                 io 0x60 = 0x290
 259                                                                 irq 0x70 = 5
 260                                                         end
 261                                                 end
 262                                         end
 263                                         device pci 1.1 on # SM 0
 264 #                                                chip drivers/generic/generic #dimm 0-0-0
 265 #                                                        device i2c 50 on end
 266 #                                                end
 267 #                                                chip drivers/generic/generic #dimm 0-0-1
 268 #                                                        device i2c 51 on end
 269 #                                                end
 270 #                                                chip drivers/generic/generic #dimm 0-1-0
 271 #                                                        device i2c 52 on end
 272 #                                                end
 273 #                                                chip drivers/generic/generic #dimm 0-1-1
 274 #                                                        device i2c 53 on end
 275 #                                                end
 276 #                                                chip drivers/generic/generic #dimm 1-0-0
 277 #                                                        device i2c 54 on end
 278 #                                                end
 279 #                                                chip drivers/generic/generic #dimm 1-0-1
 280 #                                                        device i2c 55 on end
 281 #                                                end
 282 #                                                chip drivers/generic/generic #dimm 1-1-0
 283 #                                                        device i2c 56 on end
 284 #                                                end
 285 #                                                chip drivers/generic/generic #dimm 1-1-1
 286 #                                                        device i2c 57 on end
 287 #                                                end
 288                                         end # SM
 289 #                                       device pci 1.1 on # SM 1
 290 #                                               chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
 291 #                                                       device i2c 2d on end
 292 #                                                end
 293 #                                                chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
 294 #                                                       device i2c 2e on end
 295 #                                                end
 296 #                                                chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
 297 #                                                        device i2c 2a on end
 298 #                                                end
 299 #                                                chip drivers/generic/generic # Winbond HWM 0x92
 300 #                                                        device i2c 49 on end
 301 #                                                end
 302 #                                                chip drivers/generic/generic # Winbond HWM 0x94
 303 #                                                        device i2c 4a on end
 304 #                                                end
 305 #                                       end #SM
 306                                         device pci 2.0 on end # USB 1.1
 307                                         device pci 2.1 on end # USB 2
 308                                         device pci 4.0 off end # ACI
 309                                         device pci 4.1 off end # MCI
 310                                         device pci 6.0 on end # IDE
 311                                         device pci 7.0 on end # SATA 1
 312                                         device pci 8.0 on end # SATA 0
 313                                         device pci 9.0 on  # PCI
 314                                         #       chip drivers/ati/ragexl
 315                                                 chip drivers/pci/onboard
 316                                                         device pci 7.0 on end
 317                                                         register "rom_address" = "0xfff80000" #for 512K
 318                                         #               register "rom_address" = "0xfff00000" #for 1M
 319                                                 end
 320                                         end
 321                                         device pci a.0 off end # NIC
 322                                         device pci b.0 off end # PCI E 3
 323                                         device pci c.0 off end # PCI E 2
 324                                         device pci d.0 on end # PCI E 1
 325                                         device pci e.0 on end # PCI E 0
 326                                         register "ide0_enable" = "1"
 327                                         register "ide1_enable" = "1"
 328                                         register "sata0_enable" = "1"
 329                                         register "sata1_enable" = "1"
 330                                 end
 331                         end #  device pci 18.0
 332                         device pci 18.0 on end # Link 1
 333                         device pci 18.0 on
 334                                 #  devices on link 2, link 2 == LDT 2
 335                                 chip southbridge/amd/amd8131
 336                                         # the on/off keyword is mandatory
 337                                         device pci 0.0 on end
 338                                         device pci 0.1 on end
 339                                         device pci 1.0 on
 340                                                 chip drivers/pci/onboard
 341                                                         device pci 9.0 on end
 342                                                         device pci 9.1 on end
 343                                                 end
 344                                         end
 345                                         device pci 1.1 on end
 346                                 end
 347                         end # device pci 18.0
 348                         device pci 18.1 on end
 349                         device pci 18.2 on end
 350                         device pci 18.3 on end
 351                 end #mc0
 352
 353         end # pci_domain
 354 #       chip drivers/generic/debug
 355 #                device pnp 0.0 off end # chip name
 356 #                device pnp 0.1 off end # pci_regs_all
 357 #                device pnp 0.2 off end # mem
 358 #                device pnp 0.3 off end # cpuid
 359 #                device pnp 0.4 off end # smbus_regs_all
 360 #                device pnp 0.5 off end # dual core msr
 361 #                device pnp 0.6 off end # cache size
 362 #                device pnp 0.7 off end # tsc
 363 #               device pnp 0.8 on  end # hard_reset
 364 #       end
 365 end # root_complex