src/mainboard/tyan/s2885/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "console/console.c"
  13 #include "lib/ramtest.c"
  14
  15 #include <cpu/amd/model_fxx_rev.h>
  16
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22
  23 #include "cpu/x86/lapic/boot_cpu.c"
  24 #include "northbridge/amd/amdk8/reset_test.c"
  25 #include "northbridge/amd/amdk8/debug.c"
  26 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  27
  28 #include "cpu/x86/mtrr/earlymtrr.c"
  29 #include "cpu/x86/bist.h"
  30
  31 #include "northbridge/amd/amdk8/setup_resource_map.c"
  32
  33 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  34
  35 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  36
  37 static void memreset_setup(void)
  38 {
  39    if (is_cpu_pre_c0()) {
  40         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  41    }
  42    else {
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  44    }
  45         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  46 }
  47
  48 static void memreset(int controllers, const struct mem_controller *ctrl)
  49 {
  50    if (is_cpu_pre_c0()) {
  51         udelay(800);
  52         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  53         udelay(90);
  54    }
  55 }
  56
  57 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  58 {
  59         /* nothing to do */
  60 }
  61
  62 static inline int spd_read_byte(unsigned device, unsigned address)
  63 {
  64         return smbus_read_byte(device, address);
  65 }
  66
  67 #define QRANK_DIMM_SUPPORT 1
  68
  69 #include "northbridge/amd/amdk8/raminit.c"
  70 #include "northbridge/amd/amdk8/coherent_ht.c"
  71 #include "lib/generic_sdram.c"
  72
  73  /* tyan does not want the default */
  74 #include "resourcemap.c"
  75
  76 #if CONFIG_LOGICAL_CPUS==1
  77 #define SET_NB_CFG_54 1
  78 #endif
  79 #include "cpu/amd/dualcore/dualcore.c"
  80
  81
  82
  83 #include "cpu/amd/car/post_cache_as_ram.c"
  84
  85 #include "cpu/amd/model_fxx/init_cpus.c"
  86
  87 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  88 #include "northbridge/amd/amdk8/early_ht.c"
  89
  90 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  91 {
  92         static const uint16_t spd_addr [] = {
  93                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  94                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  95 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  96                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
  97                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
  98 #endif
  99         };
 100
 101         int needs_reset;
 102         unsigned bsp_apicid = 0;
 103
 104         struct mem_controller ctrl[8];
 105         unsigned nodes;
 106
 107         if (!cpu_init_detectedx && boot_cpu()) {
 108                 /* Nothing special needs to be done to find bus 0 */
 109                 /* Allow the HT devices to be found */
 110
 111                 enumerate_ht_chain();
 112
 113                 /* Setup the amd8111 */
 114                 amd8111_enable_rom();
 115         }
 116
 117         if (bist == 0) {
 118                 bsp_apicid = init_cpus(cpu_init_detectedx);
 119         }
 120
 121 //      post_code(0x32);
 122
 123         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 124         uart_init();
 125         console_init();
 126
 127 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 128
 129         /* Halt if there was a built in self test failure */
 130         report_bist_failure(bist);
 131
 132         setup_s2885_resource_map();
 133 #if 0
 134         dump_pci_device(PCI_DEV(0, 0x18, 0));
 135         dump_pci_device(PCI_DEV(0, 0x19, 0));
 136 #endif
 137
 138         needs_reset = setup_coherent_ht_domain();
 139
 140         wait_all_core0_started();
 141 #if CONFIG_LOGICAL_CPUS==1
 142         // It is said that we should start core1 after all core0 launched
 143         start_other_cores();
 144         wait_all_other_cores_started(bsp_apicid);
 145 #endif
 146
 147         needs_reset |= ht_setup_chains_x();
 148
 149         if (needs_reset) {
 150                 print_info("ht reset -\n");
 151                 soft_reset();
 152         }
 153
 154         allow_all_aps_stop(bsp_apicid);
 155
 156         nodes = get_nodes();
 157         //It's the time to set ctrl now;
 158         fill_mem_ctrl(nodes, ctrl, spd_addr);
 159
 160         enable_smbus();
 161
 162         memreset_setup();
 163         sdram_initialize(nodes, ctrl);
 164
 165 #if 0
 166         dump_pci_devices();
 167 #endif
 168
 169         post_cache_as_ram();
 170
 171 }
 172