src/mainboard/tyan/s2885/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11
  12 #include <cpu/amd/model_fxx_rev.h>
  13
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29
  30 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  31
  32 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  33
  34 static void memreset_setup(void)
  35 {
  36    if (is_cpu_pre_c0()) {
  37         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  38    }
  39    else {
  40         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  41    }
  42         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  43 }
  44
  45 static void memreset(int controllers, const struct mem_controller *ctrl)
  46 {
  47    if (is_cpu_pre_c0()) {
  48         udelay(800);
  49         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  50         udelay(90);
  51    }
  52 }
  53
  54 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  55 {
  56         /* nothing to do */
  57 }
  58
  59 static inline int spd_read_byte(unsigned device, unsigned address)
  60 {
  61         return smbus_read_byte(device, address);
  62 }
  63
  64
  65 #include "northbridge/amd/amdk8/raminit.c"
  66 #include "northbridge/amd/amdk8/coherent_ht.c"
  67 #include "lib/generic_sdram.c"
  68
  69  /* tyan does not want the default */
  70 #include "resourcemap.c"
  71
  72 #include "cpu/amd/dualcore/dualcore.c"
  73
  74
  75
  76 #include "cpu/amd/car/post_cache_as_ram.c"
  77
  78 #include "cpu/amd/model_fxx/init_cpus.c"
  79
  80 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  81 #include "northbridge/amd/amdk8/early_ht.c"
  82
  83 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  84 {
  85         static const uint16_t spd_addr [] = {
  86                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  87                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  88 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  89                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
  90                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
  91 #endif
  92         };
  93
  94         int needs_reset;
  95         unsigned bsp_apicid = 0;
  96
  97         struct mem_controller ctrl[8];
  98         unsigned nodes;
  99
 100         if (!cpu_init_detectedx && boot_cpu()) {
 101                 /* Nothing special needs to be done to find bus 0 */
 102                 /* Allow the HT devices to be found */
 103
 104                 enumerate_ht_chain();
 105
 106                 /* Setup the amd8111 */
 107                 amd8111_enable_rom();
 108         }
 109
 110         if (bist == 0) {
 111                 bsp_apicid = init_cpus(cpu_init_detectedx);
 112         }
 113
 114 //      post_code(0x32);
 115
 116         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 117         uart_init();
 118         console_init();
 119
 120 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 121
 122         /* Halt if there was a built in self test failure */
 123         report_bist_failure(bist);
 124
 125         setup_s2885_resource_map();
 126 #if 0
 127         dump_pci_device(PCI_DEV(0, 0x18, 0));
 128         dump_pci_device(PCI_DEV(0, 0x19, 0));
 129 #endif
 130
 131         needs_reset = setup_coherent_ht_domain();
 132
 133         wait_all_core0_started();
 134 #if CONFIG_LOGICAL_CPUS==1
 135         // It is said that we should start core1 after all core0 launched
 136         start_other_cores();
 137         wait_all_other_cores_started(bsp_apicid);
 138 #endif
 139
 140         needs_reset |= ht_setup_chains_x();
 141
 142         if (needs_reset) {
 143                 print_info("ht reset -\n");
 144                 soft_reset();
 145         }
 146
 147         allow_all_aps_stop(bsp_apicid);
 148
 149         nodes = get_nodes();
 150         //It's the time to set ctrl now;
 151         fill_mem_ctrl(nodes, ctrl, spd_addr);
 152
 153         enable_smbus();
 154
 155         memreset_setup();
 156         sdram_initialize(nodes, ctrl);
 157
 158 #if 0
 159         dump_pci_devices();
 160 #endif
 161
 162         post_cache_as_ram();
 163
 164 }
 165