src/mainboard/tyan/s2885/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12
  13 #include <cpu/amd/model_fxx_rev.h>
  14
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25
  26 #include "cpu/x86/mtrr/earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #include "northbridge/amd/amdk8/setup_resource_map.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  34
  35 static void memreset_setup(void)
  36 {
  37    if (is_cpu_pre_c0()) {
  38         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  39    }
  40    else {
  41         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  42    }
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48    if (is_cpu_pre_c0()) {
  49         udelay(800);
  50         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  51         udelay(90);
  52    }
  53 }
  54
  55 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  56 {
  57         /* nothing to do */
  58 }
  59
  60 static inline int spd_read_byte(unsigned device, unsigned address)
  61 {
  62         return smbus_read_byte(device, address);
  63 }
  64
  65
  66 #include "northbridge/amd/amdk8/raminit.c"
  67 #include "northbridge/amd/amdk8/coherent_ht.c"
  68 #include "lib/generic_sdram.c"
  69
  70  /* tyan does not want the default */
  71 #include "resourcemap.c"
  72
  73 #include "cpu/amd/dualcore/dualcore.c"
  74
  75
  76
  77 #include "cpu/amd/car/post_cache_as_ram.c"
  78
  79 #include "cpu/amd/model_fxx/init_cpus.c"
  80
  81 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  82 #include "northbridge/amd/amdk8/early_ht.c"
  83
  84 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  85 {
  86         static const uint16_t spd_addr [] = {
  87                         DIMM0, DIMM2, 0, 0,
  88                         DIMM1, DIMM3, 0, 0,
  89 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  90                         DIMM4, DIMM6, 0, 0,
  91                         DIMM5, DIMM7, 0, 0,
  92 #endif
  93         };
  94
  95         int needs_reset;
  96         unsigned bsp_apicid = 0;
  97
  98         struct mem_controller ctrl[8];
  99         unsigned nodes;
 100
 101         if (!cpu_init_detectedx && boot_cpu()) {
 102                 /* Nothing special needs to be done to find bus 0 */
 103                 /* Allow the HT devices to be found */
 104
 105                 enumerate_ht_chain();
 106
 107                 /* Setup the amd8111 */
 108                 amd8111_enable_rom();
 109         }
 110
 111         if (bist == 0) {
 112                 bsp_apicid = init_cpus(cpu_init_detectedx);
 113         }
 114
 115 //      post_code(0x32);
 116
 117         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 118         uart_init();
 119         console_init();
 120
 121 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 122
 123         /* Halt if there was a built in self test failure */
 124         report_bist_failure(bist);
 125
 126         setup_s2885_resource_map();
 127 #if 0
 128         dump_pci_device(PCI_DEV(0, 0x18, 0));
 129         dump_pci_device(PCI_DEV(0, 0x19, 0));
 130 #endif
 131
 132         needs_reset = setup_coherent_ht_domain();
 133
 134         wait_all_core0_started();
 135 #if CONFIG_LOGICAL_CPUS==1
 136         // It is said that we should start core1 after all core0 launched
 137         start_other_cores();
 138         wait_all_other_cores_started(bsp_apicid);
 139 #endif
 140
 141         needs_reset |= ht_setup_chains_x();
 142
 143         if (needs_reset) {
 144                 print_info("ht reset -\n");
 145                 soft_reset();
 146         }
 147
 148         allow_all_aps_stop(bsp_apicid);
 149
 150         nodes = get_nodes();
 151         //It's the time to set ctrl now;
 152         fill_mem_ctrl(nodes, ctrl, spd_addr);
 153
 154         enable_smbus();
 155
 156         memreset_setup();
 157         sdram_initialize(nodes, ctrl);
 158
 159 #if 0
 160         dump_pci_devices();
 161 #endif
 162
 163         post_cache_as_ram();
 164
 165 }
 166