src/mainboard/tyan/s2885/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  22 #include "cpu/x86/mtrr/earlymtrr.c"
  23 #include "cpu/x86/bist.h"
  24 #include "northbridge/amd/amdk8/setup_resource_map.c"
  25 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  28
  29 static void memreset_setup(void)
  30 {
  31    if (is_cpu_pre_c0()) {
  32         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  33    }
  34    else {
  35         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  36    }
  37         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  38 }
  39
  40 static void memreset(int controllers, const struct mem_controller *ctrl)
  41 {
  42    if (is_cpu_pre_c0()) {
  43         udelay(800);
  44         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  45         udelay(90);
  46    }
  47 }
  48
  49 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  50 {
  51         /* nothing to do */
  52 }
  53
  54 static inline int spd_read_byte(unsigned device, unsigned address)
  55 {
  56         return smbus_read_byte(device, address);
  57 }
  58
  59 #include "northbridge/amd/amdk8/raminit.c"
  60 #include "northbridge/amd/amdk8/coherent_ht.c"
  61 #include "lib/generic_sdram.c"
  62 #include "resourcemap.c" /* tyan does not want the default */
  63 #include "cpu/amd/dualcore/dualcore.c"
  64 #include "cpu/amd/car/post_cache_as_ram.c"
  65 #include "cpu/amd/model_fxx/init_cpus.c"
  66 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  67 #include "northbridge/amd/amdk8/early_ht.c"
  68
  69 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  70 {
  71         static const uint16_t spd_addr [] = {
  72                         DIMM0, DIMM2, 0, 0,
  73                         DIMM1, DIMM3, 0, 0,
  74 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  75                         DIMM4, DIMM6, 0, 0,
  76                         DIMM5, DIMM7, 0, 0,
  77 #endif
  78         };
  79
  80         int needs_reset;
  81         unsigned bsp_apicid = 0;
  82
  83         struct mem_controller ctrl[8];
  84         unsigned nodes;
  85
  86         if (!cpu_init_detectedx && boot_cpu()) {
  87                 /* Nothing special needs to be done to find bus 0 */
  88                 /* Allow the HT devices to be found */
  89
  90                 enumerate_ht_chain();
  91
  92                 /* Setup the amd8111 */
  93                 amd8111_enable_rom();
  94         }
  95
  96         if (bist == 0) {
  97                 bsp_apicid = init_cpus(cpu_init_detectedx);
  98         }
  99
 100 //      post_code(0x32);
 101
 102         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 103         uart_init();
 104         console_init();
 105
 106 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 107
 108         /* Halt if there was a built in self test failure */
 109         report_bist_failure(bist);
 110
 111         setup_s2885_resource_map();
 112 #if 0
 113         dump_pci_device(PCI_DEV(0, 0x18, 0));
 114         dump_pci_device(PCI_DEV(0, 0x19, 0));
 115 #endif
 116
 117         needs_reset = setup_coherent_ht_domain();
 118
 119         wait_all_core0_started();
 120 #if CONFIG_LOGICAL_CPUS==1
 121         // It is said that we should start core1 after all core0 launched
 122         start_other_cores();
 123         wait_all_other_cores_started(bsp_apicid);
 124 #endif
 125
 126         needs_reset |= ht_setup_chains_x();
 127
 128         if (needs_reset) {
 129                 print_info("ht reset -\n");
 130                 soft_reset();
 131         }
 132
 133         allow_all_aps_stop(bsp_apicid);
 134
 135         nodes = get_nodes();
 136         //It's the time to set ctrl now;
 137         fill_mem_ctrl(nodes, ctrl, spd_addr);
 138
 139         enable_smbus();
 140
 141         memreset_setup();
 142         sdram_initialize(nodes, ctrl);
 143
 144 #if 0
 145         dump_pci_devices();
 146 #endif
 147
 148         post_cache_as_ram();
 149 }