1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 #include <cpu/amd/amdk8_sysconf.h>
9 extern unsigned char bus_isa;
10 extern unsigned char bus_8131_0;
11 extern unsigned char bus_8131_1;
12 extern unsigned char bus_8131_2;
13 extern unsigned char bus_8111_0;
14 extern unsigned char bus_8111_1;
15 extern unsigned char bus_8151_0;
16 extern unsigned char bus_8151_1;
17 extern unsigned apicid_8111;
18 extern unsigned apicid_8131_1;
19 extern unsigned apicid_8131_2;
21 extern unsigned sbdn3;
22 extern unsigned sbdn5;
27 static void *smp_write_config_table(void *v)
29 static const char sig[4] = "PCMP";
30 static const char oem[8] = "COREBOOT";
31 static const char productid[12] = "S2885 ";
32 struct mp_config_table *mc;
34 unsigned char bus_num;
38 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
39 memset(mc, 0, sizeof(*mc));
41 memcpy(mc->mpc_signature, sig, sizeof(sig));
42 mc->mpc_length = sizeof(*mc); /* initially just the header */
44 mc->mpc_checksum = 0; /* not yet computed */
45 memcpy(mc->mpc_oem, oem, sizeof(oem));
46 memcpy(mc->mpc_productid, productid, sizeof(productid));
49 mc->mpc_entry_count = 0; /* No entries yet... */
50 mc->mpc_lapic = LAPIC_ADDR;
55 smp_write_processors(mc);
60 /* define bus and isa numbers */
61 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
62 smp_write_bus(mc, bus_num, "PCI ");
64 smp_write_bus(mc, bus_isa, "ISA ");
66 /*I/O APICs: APIC ID Version State Address*/
67 smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); //8111
71 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
73 res = find_resource(dev, PCI_BASE_ADDRESS_0);
75 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
78 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
80 res = find_resource(dev, PCI_BASE_ADDRESS_0);
82 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
87 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
88 */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1);
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x2);
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_8111, 0x3);
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_8111, 0x4);
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, apicid_8111, 0x5);
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_8111, 0x6);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_8111, 0x7);
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_8111, 0x8);
97 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_8111, 0xc);
98 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd);
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13);
103 //Onboard AMD AC97 Audio
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11);
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
108 // AGP Display Adapter
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x11);
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x13);
115 //Onboard Broadcom NIC
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|i, apicid_8111, 0x10 + (0+i)%4); //16
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
132 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|i, apicid_8131_1, (2+i)%4); //26
136 //Slot 1 PCI-X 133/100/66
138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
142 //Slot 2 PCI-X 133/100/66
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (1+i)%4); //29
147 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
148 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
149 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
150 /* There is no extension information... */
152 /* Compute the checksums */
153 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
154 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
155 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
156 mc, smp_next_mpe_entry(mc));
157 return smp_next_mpe_entry(mc);
160 unsigned long write_smp_table(unsigned long addr)
163 v = smp_write_floating_table(addr);
164 return (unsigned long)smp_write_config_table(v);