1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #include <cpu/amd/amdk8_sysconf.h>
9 extern unsigned char bus_isa;
10 extern unsigned char bus_8131_0;
11 extern unsigned char bus_8131_1;
12 extern unsigned char bus_8131_2;
13 extern unsigned char bus_8111_0;
14 extern unsigned char bus_8111_1;
15 extern unsigned char bus_8151_0;
16 extern unsigned char bus_8151_1;
17 extern unsigned apicid_8111;
18 extern unsigned apicid_8131_1;
19 extern unsigned apicid_8131_2;
21 extern unsigned sbdn3;
22 extern unsigned sbdn5;
24 static void *smp_write_config_table(void *v)
26 struct mp_config_table *mc;
27 unsigned char bus_num;
30 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
32 mptable_init(mc, "S2885 ", LAPIC_ADDR);
34 smp_write_processors(mc);
39 /* define bus and isa numbers */
40 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
41 smp_write_bus(mc, bus_num, "PCI ");
43 smp_write_bus(mc, bus_isa, "ISA ");
45 /*I/O APICs: APIC ID Version State Address*/
46 smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111
50 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
52 res = find_resource(dev, PCI_BASE_ADDRESS_0);
54 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
57 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
59 res = find_resource(dev, PCI_BASE_ADDRESS_0);
61 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
66 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
68 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
70 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13);
71 //Onboard AMD AC97 Audio
72 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11);
74 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
76 // AGP Display Adapter
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x11);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x13);
83 //Onboard Broadcom NIC
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|i, apicid_8111, 0x10 + (0+i)%4); //16
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|i, apicid_8131_1, (2+i)%4); //26
104 //Slot 1 PCI-X 133/100/66
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
110 //Slot 2 PCI-X 133/100/66
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (1+i)%4); //29
115 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
116 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
117 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
118 /* There is no extension information... */
120 /* Compute the checksums */
121 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
122 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
123 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
124 mc, smp_next_mpe_entry(mc));
125 return smp_next_mpe_entry(mc);
128 unsigned long write_smp_table(unsigned long addr)
131 v = smp_write_floating_table(addr);
132 return (unsigned long)smp_write_config_table(v);