1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #include <cpu/amd/amdk8_sysconf.h>
9 extern unsigned char bus_8131_0;
10 extern unsigned char bus_8131_1;
11 extern unsigned char bus_8131_2;
12 extern unsigned char bus_8111_0;
13 extern unsigned char bus_8111_1;
14 extern unsigned char bus_8151_0;
15 extern unsigned char bus_8151_1;
16 extern unsigned apicid_8111;
17 extern unsigned apicid_8131_1;
18 extern unsigned apicid_8131_2;
20 extern unsigned sbdn3;
21 extern unsigned sbdn5;
23 static void *smp_write_config_table(void *v)
25 struct mp_config_table *mc;
28 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
30 mptable_init(mc, LAPIC_ADDR);
32 smp_write_processors(mc);
36 mptable_write_buses(mc, NULL, &bus_isa);
38 /*I/O APICs: APIC ID Version State Address*/
39 smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111
43 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
45 res = find_resource(dev, PCI_BASE_ADDRESS_0);
47 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
50 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
52 res = find_resource(dev, PCI_BASE_ADDRESS_0);
54 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
59 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
61 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
63 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13);
64 //Onboard AMD AC97 Audio
65 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
69 // AGP Display Adapter
70 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10);
73 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x11);
75 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x13);
76 //Onboard Broadcom NIC
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|i, apicid_8111, 0x10 + (0+i)%4); //16
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|i, apicid_8131_1, (2+i)%4); //26
97 //Slot 1 PCI-X 133/100/66
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
103 //Slot 2 PCI-X 133/100/66
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (1+i)%4); //29
108 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
109 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
110 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
111 /* There is no extension information... */
113 /* Compute the checksums */
114 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
115 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
116 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
117 mc, smp_next_mpe_entry(mc));
118 return smp_next_mpe_entry(mc);
121 unsigned long write_smp_table(unsigned long addr)
124 v = smp_write_floating_table(addr);
125 return (unsigned long)smp_write_config_table(v);