1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
21 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_XIP_ROM_SIZE
24 uses CONFIG_XIP_ROM_BASE
25 uses CONFIG_STACK_SIZE
27 uses CONFIG_USE_OPTION_TABLE
28 uses CONFIG_LB_CKS_RANGE_START
29 uses CONFIG_LB_CKS_RANGE_END
30 uses CONFIG_LB_CKS_LOC
31 uses CONFIG_MAINBOARD_PART_NUMBER
32 uses CONFIG_MAINBOARD_VENDOR
34 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
35 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
36 uses COREBOOT_EXTRA_VERSION
38 uses CONFIG_TTYS0_BAUD
39 uses CONFIG_TTYS0_BASE
41 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
42 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
43 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
44 uses CONFIG_CONSOLE_SERIAL8250
45 uses CONFIG_HAVE_INIT_TIMER
48 uses CONFIG_CROSS_COMPILE
52 uses CONFIG_CONSOLE_VGA
53 uses CONFIG_PCI_ROM_RUN
54 uses CONFIG_HW_MEM_HOLE_SIZEK
56 uses CONFIG_USE_DCACHE_RAM
57 uses CONFIG_DCACHE_RAM_BASE
58 uses CONFIG_DCACHE_RAM_SIZE
60 uses CONFIG_USE_PRINTK_IN_CAR
67 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
69 default CONFIG_ROM_SIZE=524288
72 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
74 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
77 ## Build code for the fallback boot
79 default CONFIG_HAVE_FALLBACK_BOOT=1
82 ## Build code to reset the motherboard from coreboot
84 default CONFIG_HAVE_HARD_RESET=1
87 ## Build code to export a programmable irq routing table
89 default CONFIG_HAVE_PIRQ_TABLE=1
90 default CONFIG_IRQ_SLOT_COUNT=15
93 ## Build code to export an x86 MP table
94 ## Useful for specifying IRQ routing values
96 default CONFIG_HAVE_MP_TABLE=1
99 ## Build code to export a CMOS option table
101 default CONFIG_HAVE_OPTION_TABLE=1
104 ## Move the default coreboot cmos range off of AMD RTC registers
106 default CONFIG_LB_CKS_RANGE_START=49
107 default CONFIG_LB_CKS_RANGE_END=122
108 default CONFIG_LB_CKS_LOC=123
111 ## Build code for SMP support
112 ## Only worry about 2 micro processors
115 default CONFIG_MAX_CPUS=4
116 default CONFIG_MAX_PHYSICAL_CPUS=2
117 default CONFIG_LOGICAL_CPUS=1
120 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
123 default CONFIG_CONSOLE_VGA=1
124 default CONFIG_PCI_ROM_RUN=1
128 ## enable CACHE_AS_RAM specifics
130 default CONFIG_USE_DCACHE_RAM=1
131 default CONFIG_DCACHE_RAM_BASE=0xcf000
132 default CONFIG_DCACHE_RAM_SIZE=0x1000
133 default CONFIG_USE_INIT=0
136 ## Build code to setup a generic IOAPIC
138 default CONFIG_IOAPIC=1
141 ## Clean up the motherboard id strings
143 default CONFIG_MAINBOARD_PART_NUMBER="S2882"
144 default CONFIG_MAINBOARD_VENDOR="Tyan"
145 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
146 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882
149 ### coreboot layout values
152 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
153 default CONFIG_ROM_IMAGE_SIZE = 65536
156 ## Use a small 8K stack
158 default CONFIG_STACK_SIZE=0x2000
161 ## Use a small 16K heap
163 default CONFIG_HEAP_SIZE=0x4000
166 ## Only use the option table in a normal image
168 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
171 ## Coreboot C code runs at this location in RAM
173 default CONFIG_RAMBASE=0x00004000
176 ## Load the payload from the ROM
178 default CONFIG_ROM_PAYLOAD = 1
181 ### Defaults of options that you may want to override in the target config file
185 ## The default compiler
187 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
191 ## Disable the gdb stub by default
193 default CONFIG_GDB_STUB=0
195 default CONFIG_USE_PRINTK_IN_CAR=1
198 ## The Serial Console
201 # To Enable the Serial Console
202 default CONFIG_CONSOLE_SERIAL8250=1
204 ## Select the serial console baud rate
205 default CONFIG_TTYS0_BAUD=115200
206 #default CONFIG_TTYS0_BAUD=57600
207 #default CONFIG_TTYS0_BAUD=38400
208 #default CONFIG_TTYS0_BAUD=19200
209 #default CONFIG_TTYS0_BAUD=9600
210 #default CONFIG_TTYS0_BAUD=4800
211 #default CONFIG_TTYS0_BAUD=2400
212 #default CONFIG_TTYS0_BAUD=1200
214 # Select the serial console base port
215 default CONFIG_TTYS0_BASE=0x3f8
217 # Select the serial protocol
218 # This defaults to 8 data bits, 1 stop bit, and no parity
219 default CONFIG_TTYS0_LCS=0x3
222 ### Select the coreboot loglevel
224 ## EMERG 1 system is unusable
225 ## ALERT 2 action must be taken immediately
226 ## CRIT 3 critical conditions
227 ## ERR 4 error conditions
228 ## WARNING 5 warning conditions
229 ## NOTICE 6 normal but significant condition
230 ## INFO 7 informational
231 ## CONFIG_DEBUG 8 debug-level messages
232 ## SPEW 9 Way too many details
234 ## Request this level of debugging output
235 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
236 ## At a maximum only compile in this level of debugging
237 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
240 ## Select power on after power fail setting
241 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"