1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
8 ## Build the objects we have code for in this directory.
15 if CONFIG_GENERATE_MP_TABLE object mptable.o end
16 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
21 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
22 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
28 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
29 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
30 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
31 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
36 ## Build our 16 bit and 32 bit coreboot entry code
38 if CONFIG_USE_FALLBACK_IMAGE
39 mainboardinit cpu/x86/16bit/entry16.inc
40 ldscript /cpu/x86/16bit/entry16.lds
43 mainboardinit cpu/x86/32bit/entry32.inc
46 ldscript /cpu/x86/32bit/entry32.lds
50 ldscript /cpu/amd/car/cache_as_ram.lds
54 ## Build our reset vector (This is where coreboot is entered)
56 if CONFIG_USE_FALLBACK_IMAGE
57 mainboardinit cpu/x86/16bit/reset16.inc
58 ldscript /cpu/x86/16bit/reset16.lds
60 mainboardinit cpu/x86/32bit/reset32.inc
61 ldscript /cpu/x86/32bit/reset32.lds
65 ## Include an id string (For safe flashing)
67 mainboardinit arch/i386/lib/id.inc
68 ldscript /arch/i386/lib/id.lds
73 mainboardinit cpu/amd/car/cache_as_ram.inc
76 ### This is the early phase of coreboot startup
77 ### Things are delicate and we test to see if we should
78 ### failover to another image.
80 if CONFIG_USE_FALLBACK_IMAGE
81 ldscript /arch/i386/lib/failover.lds
85 ### O.k. We aren't just an intermediary anymore!
94 mainboardinit ./auto.inc
98 ## Include the secondary Configuration files
102 # sample config for tyan/s2882
103 chip northbridge/amd/amdk8/root_complex
104 device apic_cluster 0 on
105 chip cpu/amd/socket_940
110 device pci_domain 0 on
111 chip northbridge/amd/amdk8
112 device pci 18.0 on # northbridge
113 # devices on link 0, link 0 == LDT 0
114 chip southbridge/amd/amd8131
115 # the on/off keyword is mandatory
117 device pci 6.0 on end # adaptec
118 device pci 6.1 on end
119 device pci 9.0 on end # broadcom 5704
120 device pci 9.1 on end
122 device pci 0.1 on end
123 device pci 1.0 on end
124 device pci 1.1 on end
126 chip southbridge/amd/amd8111
127 # this "device pci 0.0" is the parent the next one
130 device pci 0.0 on end
131 device pci 0.1 on end
132 device pci 0.2 off end
133 device pci 1.0 off end
134 device pci 5.0 on end
135 # chip drivers/ati/ragexl
136 device pci 6.0 on end
138 device pci 8.0 on end #intel 10/100
141 chip superio/winbond/w83627hf
142 device pnp 2e.0 on # Floppy
147 device pnp 2e.1 off # Parallel Port
151 device pnp 2e.2 on # Com1
155 device pnp 2e.3 off # Com2
159 device pnp 2e.5 on # Keyboard
165 device pnp 2e.6 off # CIR
168 device pnp 2e.7 off # GAME_MIDI_GIPO1
173 device pnp 2e.8 off end # GPIO2
174 device pnp 2e.9 off end # GPIO3
175 device pnp 2e.a off end # ACPI
176 device pnp 2e.b on # HW Monitor
182 device pci 1.1 on end
183 device pci 1.2 on end
184 device pci 1.3 on end
186 # chip drivers/generic/generic #dimm 0-0-0
187 # device i2c 50 on end
189 # chip drivers/generic/generic #dimm 0-0-1
190 # device i2c 51 on end
192 # chip drivers/generic/generic #dimm 0-1-0
193 # device i2c 52 on end
195 # chip drivers/generic/generic #dimm 0-1-1
196 # device i2c 53 on end
198 # chip drivers/generic/generic #dimm 1-0-0
199 # device i2c 54 on end
201 # chip drivers/generic/generic #dimm 1-0-1
202 # device i2c 55 on end
204 # chip drivers/generic/generic #dimm 1-1-0
205 # device i2c 56 on end
207 # chip drivers/generic/generic #dimm 1-1-1
208 # device i2c 57 on end
211 device pci 1.5 off end
212 device pci 1.6 off end
213 register "ide0_enable" = "1"
214 register "ide1_enable" = "1"
216 end # device pci 18.0
218 device pci 18.0 on end
219 device pci 18.0 on end
221 device pci 18.1 on end
222 device pci 18.2 on end
223 device pci 18.3 on end