src/mainboard/tyan/s2881/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11
  12 #include <cpu/amd/model_fxx_rev.h>
  13
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29
  30 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  31
  32 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  33
  34 static void memreset_setup(void)
  35 {
  36    if (is_cpu_pre_c0()) {
  37         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  38    }
  39    else {
  40         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  41    }
  42         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  43 }
  44
  45 static void memreset(int controllers, const struct mem_controller *ctrl)
  46 {
  47    if (is_cpu_pre_c0()) {
  48         udelay(800);
  49         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  50         udelay(90);
  51    }
  52 }
  53
  54 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  55 {
  56         /* nothing to do */
  57 }
  58
  59 static inline int spd_read_byte(unsigned device, unsigned address)
  60 {
  61         return smbus_read_byte(device, address);
  62 }
  63
  64 #include "northbridge/amd/amdk8/raminit.c"
  65 #include "resourcemap.c"
  66 #include "northbridge/amd/amdk8/coherent_ht.c"
  67 #include "lib/generic_sdram.c"
  68
  69 #include "cpu/amd/dualcore/dualcore.c"
  70
  71
  72
  73 #include "cpu/amd/car/post_cache_as_ram.c"
  74
  75 #include "cpu/amd/model_fxx/init_cpus.c"
  76
  77 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  78 #include "northbridge/amd/amdk8/early_ht.c"
  79
  80 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  81 {
  82         static const uint16_t spd_addr [] = {
  83                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  84                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  85 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  86                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
  87                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
  88 #endif
  89         };
  90
  91         int needs_reset;
  92         unsigned bsp_apicid = 0;
  93
  94         struct mem_controller ctrl[8];
  95         unsigned nodes;
  96
  97         if (!cpu_init_detectedx && boot_cpu()) {
  98                 /* Nothing special needs to be done to find bus 0 */
  99                 /* Allow the HT devices to be found */
 100
 101                 enumerate_ht_chain();
 102
 103                 /* Setup the amd8111 */
 104                 amd8111_enable_rom();
 105         }
 106
 107         if (bist == 0) {
 108                 bsp_apicid = init_cpus(cpu_init_detectedx);
 109         }
 110
 111 //      post_code(0x32);
 112
 113         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 114         uart_init();
 115         console_init();
 116
 117         /* Halt if there was a built in self test failure */
 118         report_bist_failure(bist);
 119
 120         setup_s2881_resource_map();
 121 #if 0
 122         dump_pci_device(PCI_DEV(0, 0x18, 0));
 123         dump_pci_device(PCI_DEV(0, 0x19, 0));
 124 #endif
 125
 126         needs_reset = setup_coherent_ht_domain();
 127
 128         wait_all_core0_started();
 129 #if CONFIG_LOGICAL_CPUS==1
 130         // It is said that we should start core1 after all core0 launched
 131         start_other_cores();
 132         wait_all_other_cores_started(bsp_apicid);
 133 #endif
 134
 135         needs_reset |= ht_setup_chains_x();
 136
 137         if (needs_reset) {
 138                 print_info("ht reset -\n");
 139                 soft_reset();
 140         }
 141
 142         enable_smbus();
 143 #if 0
 144         dump_spd_registers(&cpu[0]);
 145 #endif
 146 #if 0
 147         dump_smbus_registers();
 148 #endif
 149
 150         allow_all_aps_stop(bsp_apicid);
 151
 152         nodes = get_nodes();
 153         //It's the time to set ctrl now;
 154         fill_mem_ctrl(nodes, ctrl, spd_addr);
 155
 156         memreset_setup();
 157         sdram_initialize(nodes, ctrl);
 158
 159 #if 0
 160         dump_pci_devices();
 161 #endif
 162
 163         post_cache_as_ram();
 164 }
 165