src/mainboard/tyan/s2881/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12
  13 #include <cpu/amd/model_fxx_rev.h>
  14
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25
  26 #include "cpu/x86/mtrr/earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #include "northbridge/amd/amdk8/setup_resource_map.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  34
  35 static void memreset_setup(void)
  36 {
  37    if (is_cpu_pre_c0()) {
  38         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  39    }
  40    else {
  41         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  42    }
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48    if (is_cpu_pre_c0()) {
  49         udelay(800);
  50         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  51         udelay(90);
  52    }
  53 }
  54
  55 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  56 {
  57         /* nothing to do */
  58 }
  59
  60 static inline int spd_read_byte(unsigned device, unsigned address)
  61 {
  62         return smbus_read_byte(device, address);
  63 }
  64
  65 #include "northbridge/amd/amdk8/raminit.c"
  66 #include "resourcemap.c"
  67 #include "northbridge/amd/amdk8/coherent_ht.c"
  68 #include "lib/generic_sdram.c"
  69
  70 #include "cpu/amd/dualcore/dualcore.c"
  71
  72
  73
  74 #include "cpu/amd/car/post_cache_as_ram.c"
  75
  76 #include "cpu/amd/model_fxx/init_cpus.c"
  77
  78 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  79 #include "northbridge/amd/amdk8/early_ht.c"
  80
  81 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  82 {
  83         static const uint16_t spd_addr [] = {
  84                         DIMM0, DIMM2, 0, 0,
  85                         DIMM1, DIMM3, 0, 0,
  86 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  87                         DIMM4, DIMM6, 0, 0,
  88                         DIMM5, DIMM7, 0, 0,
  89 #endif
  90         };
  91
  92         int needs_reset;
  93         unsigned bsp_apicid = 0;
  94
  95         struct mem_controller ctrl[8];
  96         unsigned nodes;
  97
  98         if (!cpu_init_detectedx && boot_cpu()) {
  99                 /* Nothing special needs to be done to find bus 0 */
 100                 /* Allow the HT devices to be found */
 101
 102                 enumerate_ht_chain();
 103
 104                 /* Setup the amd8111 */
 105                 amd8111_enable_rom();
 106         }
 107
 108         if (bist == 0) {
 109                 bsp_apicid = init_cpus(cpu_init_detectedx);
 110         }
 111
 112 //      post_code(0x32);
 113
 114         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 115         uart_init();
 116         console_init();
 117
 118         /* Halt if there was a built in self test failure */
 119         report_bist_failure(bist);
 120
 121         setup_s2881_resource_map();
 122 #if 0
 123         dump_pci_device(PCI_DEV(0, 0x18, 0));
 124         dump_pci_device(PCI_DEV(0, 0x19, 0));
 125 #endif
 126
 127         needs_reset = setup_coherent_ht_domain();
 128
 129         wait_all_core0_started();
 130 #if CONFIG_LOGICAL_CPUS==1
 131         // It is said that we should start core1 after all core0 launched
 132         start_other_cores();
 133         wait_all_other_cores_started(bsp_apicid);
 134 #endif
 135
 136         needs_reset |= ht_setup_chains_x();
 137
 138         if (needs_reset) {
 139                 print_info("ht reset -\n");
 140                 soft_reset();
 141         }
 142
 143         enable_smbus();
 144 #if 0
 145         dump_spd_registers(&cpu[0]);
 146 #endif
 147 #if 0
 148         dump_smbus_registers();
 149 #endif
 150
 151         allow_all_aps_stop(bsp_apicid);
 152
 153         nodes = get_nodes();
 154         //It's the time to set ctrl now;
 155         fill_mem_ctrl(nodes, ctrl, spd_addr);
 156
 157         memreset_setup();
 158         sdram_initialize(nodes, ctrl);
 159
 160 #if 0
 161         dump_pci_devices();
 162 #endif
 163
 164         post_cache_as_ram();
 165 }
 166