src/mainboard/tyan/s2881/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  22 #include "cpu/x86/mtrr/earlymtrr.c"
  23 #include "cpu/x86/bist.h"
  24 #include "northbridge/amd/amdk8/setup_resource_map.c"
  25 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  28
  29 static void memreset_setup(void)
  30 {
  31    if (is_cpu_pre_c0())
  32         outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  33    else
  34         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  35    outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  36 }
  37
  38 static void memreset(int controllers, const struct mem_controller *ctrl)
  39 {
  40    if (is_cpu_pre_c0()) {
  41         udelay(800);
  42         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  43         udelay(90);
  44    }
  45 }
  46
  47 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  48
  49 static inline int spd_read_byte(unsigned device, unsigned address)
  50 {
  51         return smbus_read_byte(device, address);
  52 }
  53
  54 #include "northbridge/amd/amdk8/raminit.c"
  55 #include "resourcemap.c"
  56 #include "northbridge/amd/amdk8/coherent_ht.c"
  57 #include "lib/generic_sdram.c"
  58 #include "cpu/amd/dualcore/dualcore.c"
  59 #include "cpu/amd/car/post_cache_as_ram.c"
  60 #include "cpu/amd/model_fxx/init_cpus.c"
  61 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  62 #include "northbridge/amd/amdk8/early_ht.c"
  63
  64 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  65 {
  66         static const uint16_t spd_addr [] = {
  67                 DIMM0, DIMM2, 0, 0,
  68                 DIMM1, DIMM3, 0, 0,
  69 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  70                 DIMM4, DIMM6, 0, 0,
  71                 DIMM5, DIMM7, 0, 0,
  72 #endif
  73         };
  74
  75         int needs_reset;
  76         unsigned bsp_apicid = 0, nodes;
  77         struct mem_controller ctrl[8];
  78
  79         if (!cpu_init_detectedx && boot_cpu()) {
  80                 /* Nothing special needs to be done to find bus 0 */
  81                 /* Allow the HT devices to be found */
  82                 enumerate_ht_chain();
  83                 amd8111_enable_rom();
  84         }
  85
  86         if (bist == 0)
  87                 bsp_apicid = init_cpus(cpu_init_detectedx);
  88
  89 //      post_code(0x32);
  90
  91         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  92         uart_init();
  93         console_init();
  94
  95         /* Halt if there was a built in self test failure */
  96         report_bist_failure(bist);
  97
  98         setup_s2881_resource_map();
  99 #if 0
 100         dump_pci_device(PCI_DEV(0, 0x18, 0));
 101         dump_pci_device(PCI_DEV(0, 0x19, 0));
 102 #endif
 103
 104         needs_reset = setup_coherent_ht_domain();
 105
 106         wait_all_core0_started();
 107 #if CONFIG_LOGICAL_CPUS==1
 108         // It is said that we should start core1 after all core0 launched
 109         start_other_cores();
 110         wait_all_other_cores_started(bsp_apicid);
 111 #endif
 112
 113         needs_reset |= ht_setup_chains_x();
 114
 115         if (needs_reset) {
 116                 print_info("ht reset -\n");
 117                 soft_reset();
 118         }
 119
 120         enable_smbus();
 121 #if 0
 122         dump_spd_registers(&cpu[0]);
 123         dump_smbus_registers();
 124 #endif
 125
 126         allow_all_aps_stop(bsp_apicid);
 127
 128         nodes = get_nodes();
 129         //It's the time to set ctrl now;
 130         fill_mem_ctrl(nodes, ctrl, spd_addr);
 131
 132         memreset_setup();
 133         sdram_initialize(nodes, ctrl);
 134
 135 #if 0
 136         dump_pci_devices();
 137 #endif
 138
 139         post_cache_as_ram();
 140 }