1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #include <cpu/amd/amdk8_sysconf.h>
9 extern unsigned char bus_8131_0;
10 extern unsigned char bus_8131_1;
11 extern unsigned char bus_8131_2;
12 extern unsigned char bus_8111_0;
13 extern unsigned char bus_8111_1;
14 extern unsigned apicid_8111;
15 extern unsigned apicid_8131_1;
16 extern unsigned apicid_8131_2;
18 extern unsigned sbdn3;
20 static void *smp_write_config_table(void *v)
22 struct mp_config_table *mc;
25 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
27 mptable_init(mc, LAPIC_ADDR);
29 smp_write_processors(mc);
33 mptable_write_buses(mc, NULL, &bus_isa);
35 /*I/O APICs: APIC ID Version State Address*/
36 smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
40 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
42 res = find_resource(dev, PCI_BASE_ADDRESS_0);
44 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
47 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
49 res = find_resource(dev, PCI_BASE_ADDRESS_0);
51 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
57 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
59 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
61 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13);
63 //On Board AMD USB ???
64 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
66 //On Board ATI Display Adapter
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
69 //On Board SI Serial ATA
70 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
74 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
77 //On Board NIC and adaptec scsi
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|i, apicid_8131_1, (0+i)%4); //24
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (0+i)%4); //24
83 //Slot 1 PCI-X 133/100/66 or Side 1 on raiser card
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
88 //Slot 1 PCI-X 133/100/66, Side 2 on raiser card
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (1+i)%4); //28
96 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
97 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
98 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
99 /* There is no extension information... */
101 /* Compute the checksums */
102 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
103 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
104 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
105 mc, smp_next_mpe_entry(mc));
106 return smp_next_mpe_entry(mc);
109 unsigned long write_smp_table(unsigned long addr)
112 v = smp_write_floating_table(addr);
113 return (unsigned long)smp_write_config_table(v);