1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_IRQ_SLOT_COUNT
8 uses CONFIG_HAVE_OPTION_TABLE
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
14 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_IMAGE_SIZE
18 uses CONFIG_ROM_SECTION_SIZE
19 uses CONFIG_ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
24 uses CONFIG_PAYLOAD_SIZE
26 uses CONFIG_XIP_ROM_SIZE
27 uses CONFIG_XIP_ROM_BASE
28 uses CONFIG_STACK_SIZE
30 uses CONFIG_USE_OPTION_TABLE
31 uses CONFIG_LB_CKS_RANGE_START
32 uses CONFIG_LB_CKS_RANGE_END
33 uses CONFIG_LB_CKS_LOC
34 uses CONFIG_MAINBOARD_PART_NUMBER
35 uses CONFIG_MAINBOARD_VENDOR
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
38 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
39 uses COREBOOT_EXTRA_VERSION
41 uses CONFIG_TTYS0_BAUD
42 uses CONFIG_TTYS0_BASE
44 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
45 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
46 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_SERIAL8250
48 uses CONFIG_HAVE_INIT_TIMER
51 uses CONFIG_CROSS_COMPILE
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses CONFIG_HW_MEM_HOLE_SIZEK
59 uses CONFIG_HT_CHAIN_UNITID_BASE
60 uses CONFIG_HT_CHAIN_END_UNITID_BASE
61 uses CONFIG_SB_HT_CHAIN_ON_BUS0
62 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
64 uses CONFIG_USE_DCACHE_RAM
65 uses CONFIG_DCACHE_RAM_BASE
66 uses CONFIG_DCACHE_RAM_SIZE
68 uses CONFIG_USE_PRINTK_IN_CAR
75 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
77 default CONFIG_ROM_SIZE=524288
80 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
82 #default CONFIG_FALLBACK_SIZE=131072
84 default CONFIG_FALLBACK_SIZE=0x40000
87 ## Build code for the fallback boot
89 default CONFIG_HAVE_FALLBACK_BOOT=1
92 ## Build code to reset the motherboard from coreboot
94 default CONFIG_HAVE_HARD_RESET=1
97 ## Build code to export a programmable irq routing table
99 default CONFIG_HAVE_PIRQ_TABLE=1
100 default CONFIG_IRQ_SLOT_COUNT=9
103 ## Build code to export an x86 MP table
104 ## Useful for specifying IRQ routing values
106 default CONFIG_HAVE_MP_TABLE=1
109 ## Build code to export a CMOS option table
111 default CONFIG_HAVE_OPTION_TABLE=1
114 ## Move the default coreboot cmos range off of AMD RTC registers
116 default CONFIG_LB_CKS_RANGE_START=49
117 default CONFIG_LB_CKS_RANGE_END=122
118 default CONFIG_LB_CKS_LOC=123
121 ## Build code for SMP support
122 ## Only worry about 2 micro processors
125 default CONFIG_MAX_CPUS=4
126 default CONFIG_MAX_PHYSICAL_CPUS=2
127 default CONFIG_LOGICAL_CPUS=1
129 ##HT Unit ID offset, default is 1, the typical one
130 default CONFIG_HT_CHAIN_UNITID_BASE=0x0a
132 ##real SB Unit ID, default is 0x20, mean dont touch it at last
133 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06
135 #make the SB HT chain on bus 0, default is not (0)
136 default CONFIG_SB_HT_CHAIN_ON_BUS0=0
138 ##only offset for SB chain?, default is yes(1)
139 #default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
142 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
145 default CONFIG_CONSOLE_VGA=1
146 default CONFIG_PCI_ROM_RUN=1
150 ## enable CACHE_AS_RAM specifics
152 default CONFIG_USE_DCACHE_RAM=1
153 default CONFIG_DCACHE_RAM_BASE=0xcf000
154 default CONFIG_DCACHE_RAM_SIZE=0x1000
155 default CONFIG_USE_INIT=0
158 ## Build code to setup a generic IOAPIC
160 default CONFIG_IOAPIC=1
163 ## Clean up the motherboard id strings
165 default CONFIG_MAINBOARD_PART_NUMBER="s2881"
166 default CONFIG_MAINBOARD_VENDOR="Tyan"
167 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
168 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
171 ### coreboot layout values
174 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
175 default CONFIG_ROM_IMAGE_SIZE = 65536
178 ## Use a small 8K stack
180 default CONFIG_STACK_SIZE=0x2000
183 ## Use a small 16K heap
185 default CONFIG_HEAP_SIZE=0x4000
188 ## Only use the option table in a normal image
190 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
193 ## Coreboot C code runs at this location in RAM
195 default CONFIG_RAMBASE=0x00004000
198 ## Load the payload from the ROM
200 default CONFIG_ROM_PAYLOAD = 1
203 ### Defaults of options that you may want to override in the target config file
207 ## The default compiler
209 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
213 ## Disable the gdb stub by default
215 default CONFIG_GDB_STUB=0
217 default CONFIG_USE_PRINTK_IN_CAR=1
220 ## The Serial Console
223 # To Enable the Serial Console
224 default CONFIG_CONSOLE_SERIAL8250=1
226 ## Select the serial console baud rate
227 default CONFIG_TTYS0_BAUD=115200
228 #default CONFIG_TTYS0_BAUD=57600
229 #default CONFIG_TTYS0_BAUD=38400
230 #default CONFIG_TTYS0_BAUD=19200
231 #default CONFIG_TTYS0_BAUD=9600
232 #default CONFIG_TTYS0_BAUD=4800
233 #default CONFIG_TTYS0_BAUD=2400
234 #default CONFIG_TTYS0_BAUD=1200
236 # Select the serial console base port
237 default CONFIG_TTYS0_BASE=0x3f8
239 # Select the serial protocol
240 # This defaults to 8 data bits, 1 stop bit, and no parity
241 default CONFIG_TTYS0_LCS=0x3
244 ### Select the coreboot loglevel
246 ## EMERG 1 system is unusable
247 ## ALERT 2 action must be taken immediately
248 ## CRIT 3 critical conditions
249 ## ERR 4 error conditions
250 ## WARNING 5 warning conditions
251 ## NOTICE 6 normal but significant condition
252 ## INFO 7 informational
253 ## CONFIG_DEBUG 8 debug-level messages
254 ## SPEW 9 Way too many details
256 ## Request this level of debugging output
257 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
258 ## At a maximum only compile in this level of debugging
259 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
262 ## Select power on after power fail setting
263 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
270 default CONFIG_CBFS=0