1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
8 ## Build the objects we have code for in this directory.
15 if CONFIG_GENERATE_MP_TABLE object mptable.o end
16 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
21 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
22 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
28 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
29 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
30 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
31 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
36 ## Build our 16 bit and 32 bit coreboot entry code
38 if CONFIG_USE_FALLBACK_IMAGE
39 mainboardinit cpu/x86/16bit/entry16.inc
40 ldscript /cpu/x86/16bit/entry16.lds
43 mainboardinit cpu/x86/32bit/entry32.inc
46 ldscript /cpu/x86/32bit/entry32.lds
50 ldscript /cpu/amd/car/cache_as_ram.lds
54 ## Build our reset vector (This is where coreboot is entered)
56 if CONFIG_USE_FALLBACK_IMAGE
57 mainboardinit cpu/x86/16bit/reset16.inc
58 ldscript /cpu/x86/16bit/reset16.lds
60 mainboardinit cpu/x86/32bit/reset32.inc
61 ldscript /cpu/x86/32bit/reset32.lds
65 ## Include an id string (For safe flashing)
67 mainboardinit arch/i386/lib/id.inc
68 ldscript /arch/i386/lib/id.lds
73 mainboardinit cpu/amd/car/cache_as_ram.inc
76 ### This is the early phase of coreboot startup
77 ### Things are delicate and we test to see if we should
78 ### failover to another image.
80 if CONFIG_USE_FALLBACK_IMAGE
81 ldscript /arch/i386/lib/failover.lds
85 ### O.k. We aren't just an intermediary anymore!
94 mainboardinit ./auto.inc
98 ## Include the secondary Configuration files
102 # sample config for tyan/s2881
103 chip northbridge/amd/amdk8/root_complex
104 device apic_cluster 0 on
105 chip cpu/amd/socket_940
109 device pci_domain 0 on
110 chip northbridge/amd/amdk8
111 device pci 18.0 on end # LDT0
112 device pci 18.0 on end # LDT1
113 device pci 18.0 on # northbridge
114 # devices on link 2, link 2 == LDT 2
115 chip southbridge/amd/amd8131
116 # the on/off keyword is mandatory
118 chip drivers/pci/onboard
119 device pci 9.0 on end # Broadcom 5704
120 device pci 9.1 on end
122 chip drivers/pci/onboard
123 device pci a.0 on end # Adaptic
124 device pci a.1 on end
127 device pci 0.1 on end
128 device pci 1.0 on end
129 device pci 1.1 on end
131 chip southbridge/amd/amd8111
132 # this "device pci 0.0" is the parent the next one
135 device pci 0.0 on end
136 device pci 0.1 on end
137 device pci 0.2 off end
138 device pci 1.0 off end
139 chip drivers/pci/onboard
140 device pci 5.0 on end # SiI
142 chip drivers/pci/onboard
143 device pci 6.0 on end
144 register "rom_address" = "0xfff80000"
148 chip superio/winbond/w83627hf
149 device pnp 2e.0 on # Floppy
154 device pnp 2e.1 off # Parallel Port
158 device pnp 2e.2 on # Com1
162 device pnp 2e.3 off # Com2
166 device pnp 2e.5 on # Keyboard
172 device pnp 2e.6 off # CIR
175 device pnp 2e.7 off # GAME_MIDI_GIPO1
180 device pnp 2e.8 off end # GPIO2
181 device pnp 2e.9 off end # GPIO3
182 device pnp 2e.a off end # ACPI
183 device pnp 2e.b on # HW Monitor
189 device pci 1.1 on end
190 device pci 1.2 on end
192 chip drivers/generic/generic #dimm 0-0-0
195 chip drivers/generic/generic #dimm 0-0-1
198 chip drivers/generic/generic #dimm 0-1-0
201 chip drivers/generic/generic #dimm 0-1-1
204 chip drivers/generic/generic #dimm 1-0-0
207 chip drivers/generic/generic #dimm 1-0-1
210 chip drivers/generic/generic #dimm 1-1-0
213 chip drivers/generic/generic #dimm 1-1-1
216 chip drivers/i2c/adm1027 # ADT7463A CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3
219 chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN
222 chip drivers/generic/generic # Winbond HWM 0x92
225 chip drivers/generic/generic # Winbond HWM 0x94
229 device pci 1.5 off end
230 device pci 1.6 off end
231 register "ide0_enable" = "1"
232 register "ide1_enable" = "1"
234 end # device pci 18.0
236 device pci 18.1 on end
237 device pci 18.2 on end
238 device pci 18.3 on end