1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_IRQ_SLOT_COUNT
8 uses CONFIG_HAVE_OPTION_TABLE
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
14 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_IMAGE_SIZE
18 uses CONFIG_ROM_SECTION_SIZE
19 uses CONFIG_ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
24 uses CONFIG_PAYLOAD_SIZE
26 uses CONFIG_XIP_ROM_SIZE
27 uses CONFIG_XIP_ROM_BASE
28 uses CONFIG_STACK_SIZE
30 uses CONFIG_USE_OPTION_TABLE
31 uses CONFIG_LB_CKS_RANGE_START
32 uses CONFIG_LB_CKS_RANGE_END
33 uses CONFIG_LB_CKS_LOC
34 uses CONFIG_MAINBOARD_PART_NUMBER
35 uses CONFIG_MAINBOARD_VENDOR
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
38 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
39 uses COREBOOT_EXTRA_VERSION
41 uses CONFIG_TTYS0_BAUD
42 uses CONFIG_TTYS0_BASE
44 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
45 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
46 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_SERIAL8250
48 uses CONFIG_HAVE_INIT_TIMER
51 uses CONFIG_CROSS_COMPILE
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses CONFIG_HW_MEM_HOLE_SIZEK
59 uses CONFIG_USE_DCACHE_RAM
60 uses CONFIG_DCACHE_RAM_BASE
61 uses CONFIG_DCACHE_RAM_SIZE
63 uses CONFIG_USE_PRINTK_IN_CAR
70 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
72 default CONFIG_ROM_SIZE=524288
75 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
77 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
81 ## Build code for the fallback boot
83 default CONFIG_HAVE_FALLBACK_BOOT=1
86 ## Build code to reset the motherboard from coreboot
88 default CONFIG_HAVE_HARD_RESET=1
91 ## Build code to export a programmable irq routing table
93 default CONFIG_HAVE_PIRQ_TABLE=1
94 default CONFIG_IRQ_SLOT_COUNT=13
97 ## Build code to export an x86 MP table
98 ## Useful for specifying IRQ routing values
100 default CONFIG_HAVE_MP_TABLE=1
103 ## Build code to export a CMOS option table
105 default CONFIG_HAVE_OPTION_TABLE=1
108 ## Move the default coreboot cmos range off of AMD RTC registers
110 default CONFIG_LB_CKS_RANGE_START=49
111 default CONFIG_LB_CKS_RANGE_END=122
112 default CONFIG_LB_CKS_LOC=123
115 ## Build code for SMP support
116 ## Only worry about 2 micro processors
119 default CONFIG_MAX_CPUS=4
120 default CONFIG_MAX_PHYSICAL_CPUS=2
121 default CONFIG_LOGICAL_CPUS=1
124 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
127 default CONFIG_CONSOLE_VGA=1
128 default CONFIG_PCI_ROM_RUN=1
132 ## enable CACHE_AS_RAM specifics
134 default CONFIG_USE_DCACHE_RAM=1
135 default CONFIG_DCACHE_RAM_BASE=0xcf000
136 default CONFIG_DCACHE_RAM_SIZE=0x1000
137 default CONFIG_USE_INIT=0
140 ## Build code to setup a generic IOAPIC
142 default CONFIG_IOAPIC=1
145 ## Clean up the motherboard id strings
147 default CONFIG_MAINBOARD_PART_NUMBER="s2875"
148 default CONFIG_MAINBOARD_VENDOR="Tyan"
149 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
150 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875
153 ### coreboot layout values
156 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
157 default CONFIG_ROM_IMAGE_SIZE = 65536
160 ## Use a small 8K stack
162 default CONFIG_STACK_SIZE=0x2000
165 ## Use a small 16K heap
167 default CONFIG_HEAP_SIZE=0x4000
170 ## Only use the option table in a normal image
172 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
175 ## Coreboot C code runs at this location in RAM
177 default CONFIG_RAMBASE=0x00004000
180 ## Load the payload from the ROM
182 default CONFIG_ROM_PAYLOAD = 1
185 ### Defaults of options that you may want to override in the target config file
189 ## The default compiler
191 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
195 ## Disable the gdb stub by default
197 default CONFIG_GDB_STUB=0
199 default CONFIG_USE_PRINTK_IN_CAR=1
202 ## The Serial Console
205 # To Enable the Serial Console
206 default CONFIG_CONSOLE_SERIAL8250=1
208 ## Select the serial console baud rate
209 default CONFIG_TTYS0_BAUD=115200
210 #default CONFIG_TTYS0_BAUD=57600
211 #default CONFIG_TTYS0_BAUD=38400
212 #default CONFIG_TTYS0_BAUD=19200
213 #default CONFIG_TTYS0_BAUD=9600
214 #default CONFIG_TTYS0_BAUD=4800
215 #default CONFIG_TTYS0_BAUD=2400
216 #default CONFIG_TTYS0_BAUD=1200
218 # Select the serial console base port
219 default CONFIG_TTYS0_BASE=0x3f8
221 # Select the serial protocol
222 # This defaults to 8 data bits, 1 stop bit, and no parity
223 default CONFIG_TTYS0_LCS=0x3
226 ### Select the coreboot loglevel
228 ## EMERG 1 system is unusable
229 ## ALERT 2 action must be taken immediately
230 ## CRIT 3 critical conditions
231 ## ERR 4 error conditions
232 ## WARNING 5 warning conditions
233 ## NOTICE 6 normal but significant condition
234 ## INFO 7 informational
235 ## CONFIG_DEBUG 8 debug-level messages
236 ## SPEW 9 Way too many details
238 ## Request this level of debugging output
239 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
240 ## At a maximum only compile in this level of debugging
241 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
244 ## Select power on after power fail setting
245 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
252 default CONFIG_CBFS=1