1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_PAYLOAD_SIZE
25 uses CONFIG_XIP_ROM_SIZE
26 uses CONFIG_XIP_ROM_BASE
27 uses CONFIG_STACK_SIZE
29 uses CONFIG_USE_OPTION_TABLE
30 uses CONFIG_LB_CKS_RANGE_START
31 uses CONFIG_LB_CKS_RANGE_END
32 uses CONFIG_LB_CKS_LOC
33 uses CONFIG_MAINBOARD_PART_NUMBER
34 uses CONFIG_MAINBOARD_VENDOR
36 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
40 uses CONFIG_TTYS0_BAUD
41 uses CONFIG_TTYS0_BASE
43 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
44 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
45 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
46 uses CONFIG_CONSOLE_SERIAL8250
47 uses CONFIG_HAVE_INIT_TIMER
50 uses CONFIG_CROSS_COMPILE
54 uses CONFIG_CONSOLE_VGA
55 uses CONFIG_PCI_ROM_RUN
56 uses CONFIG_HW_MEM_HOLE_SIZEK
58 uses CONFIG_USE_DCACHE_RAM
59 uses CONFIG_DCACHE_RAM_BASE
60 uses CONFIG_DCACHE_RAM_SIZE
62 uses CONFIG_USE_PRINTK_IN_CAR
69 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
71 default CONFIG_ROM_SIZE=524288
74 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
76 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
80 ## Build code for the fallback boot
82 default CONFIG_HAVE_FALLBACK_BOOT=1
85 ## Build code to reset the motherboard from coreboot
87 default CONFIG_HAVE_HARD_RESET=1
90 ## Build code to export a programmable irq routing table
92 default CONFIG_HAVE_PIRQ_TABLE=1
93 default CONFIG_IRQ_SLOT_COUNT=13
96 ## Build code to export an x86 MP table
97 ## Useful for specifying IRQ routing values
99 default CONFIG_HAVE_MP_TABLE=1
102 ## Build code to export a CMOS option table
104 default CONFIG_HAVE_OPTION_TABLE=1
107 ## Move the default coreboot cmos range off of AMD RTC registers
109 default CONFIG_LB_CKS_RANGE_START=49
110 default CONFIG_LB_CKS_RANGE_END=122
111 default CONFIG_LB_CKS_LOC=123
114 ## Build code for SMP support
115 ## Only worry about 2 micro processors
118 default CONFIG_MAX_CPUS=4
119 default CONFIG_MAX_PHYSICAL_CPUS=2
120 default CONFIG_LOGICAL_CPUS=1
123 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
126 default CONFIG_CONSOLE_VGA=1
127 default CONFIG_PCI_ROM_RUN=1
131 ## enable CACHE_AS_RAM specifics
133 default CONFIG_USE_DCACHE_RAM=1
134 default CONFIG_DCACHE_RAM_BASE=0xcf000
135 default CONFIG_DCACHE_RAM_SIZE=0x1000
136 default CONFIG_USE_INIT=0
139 ## Build code to setup a generic IOAPIC
141 default CONFIG_IOAPIC=1
144 ## Clean up the motherboard id strings
146 default CONFIG_MAINBOARD_PART_NUMBER="s2875"
147 default CONFIG_MAINBOARD_VENDOR="Tyan"
148 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
149 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875
152 ### coreboot layout values
155 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
156 default CONFIG_ROM_IMAGE_SIZE = 65536
159 ## Use a small 8K stack
161 default CONFIG_STACK_SIZE=0x2000
164 ## Use a small 16K heap
166 default CONFIG_HEAP_SIZE=0x4000
169 ## Only use the option table in a normal image
171 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
174 ## Coreboot C code runs at this location in RAM
176 default CONFIG_RAMBASE=0x00004000
179 ## Load the payload from the ROM
181 default CONFIG_ROM_PAYLOAD = 1
184 ### Defaults of options that you may want to override in the target config file
188 ## The default compiler
190 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
194 ## Disable the gdb stub by default
196 default CONFIG_GDB_STUB=0
198 default CONFIG_USE_PRINTK_IN_CAR=1
201 ## The Serial Console
204 # To Enable the Serial Console
205 default CONFIG_CONSOLE_SERIAL8250=1
207 ## Select the serial console baud rate
208 default CONFIG_TTYS0_BAUD=115200
209 #default CONFIG_TTYS0_BAUD=57600
210 #default CONFIG_TTYS0_BAUD=38400
211 #default CONFIG_TTYS0_BAUD=19200
212 #default CONFIG_TTYS0_BAUD=9600
213 #default CONFIG_TTYS0_BAUD=4800
214 #default CONFIG_TTYS0_BAUD=2400
215 #default CONFIG_TTYS0_BAUD=1200
217 # Select the serial console base port
218 default CONFIG_TTYS0_BASE=0x3f8
220 # Select the serial protocol
221 # This defaults to 8 data bits, 1 stop bit, and no parity
222 default CONFIG_TTYS0_LCS=0x3
225 ### Select the coreboot loglevel
227 ## EMERG 1 system is unusable
228 ## ALERT 2 action must be taken immediately
229 ## CRIT 3 critical conditions
230 ## ERR 4 error conditions
231 ## WARNING 5 warning conditions
232 ## NOTICE 6 normal but significant condition
233 ## INFO 7 informational
234 ## CONFIG_DEBUG 8 debug-level messages
235 ## SPEW 9 Way too many details
237 ## Request this level of debugging output
238 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
239 ## At a maximum only compile in this level of debugging
240 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
243 ## Select power on after power fail setting
244 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"