src/mainboard/tyan/s2875/Config.lb

   1 ## XIP_ROM_SIZE must be a power of 2.
   2 default XIP_ROM_SIZE = 64 * 1024
   3 include /config/nofailovercalculation.lb
   4
   5 arch i386 end
   6
   7 ##
   8 ## Build the objects we have code for in this directory.
   9 ##
  10
  11 driver mainboard.o
  12
  13 #dir /drivers/si/3114
  14
  15 if HAVE_MP_TABLE object mptable.o end
  16 if HAVE_PIRQ_TABLE object irq_tables.o end
  17
  18 if CONFIG_USE_INIT
  19
  20 makerule ./auto.o
  21         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  22         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  23 end
  24
  25 else
  26
  27 makerule ./auto.inc
  28         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  29         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  30         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  31         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  32 end
  33
  34 end
  35 ##
  36 ## Build our 16 bit and 32 bit coreboot entry code
  37 ##
  38 if USE_FALLBACK_IMAGE
  39         mainboardinit cpu/x86/16bit/entry16.inc
  40         ldscript /cpu/x86/16bit/entry16.lds
  41 end
  42
  43 mainboardinit cpu/x86/32bit/entry32.inc
  44
  45         if CONFIG_USE_INIT
  46                 ldscript /cpu/x86/32bit/entry32.lds
  47         end
  48
  49         if CONFIG_USE_INIT
  50                 ldscript      /cpu/amd/car/cache_as_ram.lds
  51         end
  52
  53 ##
  54 ## Build our reset vector (This is where coreboot is entered)
  55 ##
  56 if USE_FALLBACK_IMAGE
  57         mainboardinit cpu/x86/16bit/reset16.inc
  58         ldscript /cpu/x86/16bit/reset16.lds
  59 else
  60         mainboardinit cpu/x86/32bit/reset32.inc
  61         ldscript /cpu/x86/32bit/reset32.lds
  62 end
  63
  64 ##
  65 ## Include an id string (For safe flashing)
  66 ##
  67 mainboardinit arch/i386/lib/id.inc
  68 ldscript /arch/i386/lib/id.lds
  69
  70 ##
  71 ## Setup Cache-As-Ram
  72 ##
  73 mainboardinit cpu/amd/car/cache_as_ram.inc
  74
  75 ###
  76 ### This is the early phase of coreboot startup
  77 ### Things are delicate and we test to see if we should
  78 ### failover to another image.
  79 ###
  80 if USE_FALLBACK_IMAGE
  81        ldscript /arch/i386/lib/failover.lds
  82 end
  83
  84 ###
  85 ### O.k. We aren't just an intermediary anymore!
  86 ###
  87
  88 ##
  89 ## Setup RAM
  90 ##
  91 if CONFIG_USE_INIT
  92 initobject auto.o
  93 else
  94 mainboardinit ./auto.inc
  95 end
  96
  97 ##
  98 ## Include the secondary Configuration files
  99 ##
 100 config chip.h
 101
 102 # sample config for tyan/s2875
 103 chip northbridge/amd/amdk8/root_complex
 104         device apic_cluster 0 on
 105                 chip cpu/amd/socket_940
 106                         device apic 0 on end
 107                 end
 108         end
 109         device pci_domain 0 on
 110                 chip northbridge/amd/amdk8
 111                         device pci 18.0 on #  northbridge
 112                                 #  devices on link 0, link 0 == LDT 0
 113                                 chip southbridge/amd/amd8151
 114                                         # the on/off keyword is mandatory
 115                                         device pci 0.0 on end
 116                                         device pci 1.0 on end
 117                                 end
 118                                 chip southbridge/amd/amd8111
 119                                         # this "device pci 0.0" is the parent the next one
 120                                         # PCI bridge
 121                                         device pci 0.0 on
 122                                                 device pci 0.0 on end
 123                                                 device pci 0.1 on end
 124                                                 device pci 0.2 off end
 125                                                 device pci 1.0 off end
 126                                                 chip drivers/pci/onboard
 127                                                         device pci 5.0 on end
 128                                                         register "rom_address" = "0xfff80000"
 129                                                 end
 130                                         end
 131                                         device pci 1.0 on
 132                                                 chip superio/winbond/w83627hf
 133                                                         device pnp 2e.0 on #  Floppy
 134                                                                 io 0x60 = 0x3f0
 135                                                                 irq 0x70 = 6
 136                                                                 drq 0x74 = 2
 137                                                         end
 138                                                         device pnp 2e.1 off #  Parallel Port
 139                                                                 io 0x60 = 0x378
 140                                                                 irq 0x70 = 7
 141                                                         end
 142                                                         device pnp 2e.2 on #  Com1
 143                                                                 io 0x60 = 0x3f8
 144                                                                 irq 0x70 = 4
 145                                                         end
 146                                                         device pnp 2e.3 off #  Com2
 147                                                                 io 0x60 = 0x2f8
 148                                                                 irq 0x70 = 3
 149                                                         end
 150                                                         device pnp 2e.5 on #  Keyboard
 151                                                                 io 0x60 = 0x60
 152                                                                 io 0x62 = 0x64
 153                                                                 irq 0x70 = 1
 154                                                                 irq 0x72 = 12
 155                                                         end
 156                                                         device pnp 2e.6 off #  CIR
 157                                                                 io 0x60 = 0x100
 158                                                         end
 159                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 160                                                                 io 0x60 = 0x220
 161                                                                 io 0x62 = 0x300
 162                                                                 irq 0x70 = 9
 163                                                         end
 164                                                         device pnp 2e.8 off end #  GPIO2
 165                                                         device pnp 2e.9 off end #  GPIO3
 166                                                         device pnp 2e.a off end #  ACPI
 167                                                         device pnp 2e.b on #  HW Monitor
 168                                                                 io 0x60 = 0x290
 169                                                                 irq 0x70 = 5
 170                                                         end
 171                                                 end
 172                                         end
 173                                         device pci 1.1 on end
 174                                         device pci 1.2 on end
 175                                         device pci 1.3 on end
 176                                         device pci 1.5 on end
 177                                         device pci 1.6 off end
 178                                         register "ide0_enable" = "1"
 179                                         register "ide1_enable" = "1"
 180                                 end
 181                         end #  device pci 18.0
 182
 183                         device pci 18.0 on end
 184                         device pci 18.0 on end
 185
 186                         device pci 18.1 on end
 187                         device pci 18.2 on end
 188                         device pci 18.3 on end
 189                 end
 190         end
 191 end
 192