src/mainboard/tyan/s2850/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11 #include <lib.h>
  12 #include <spd.h>
  13 #include <cpu/amd/model_fxx_rev.h>
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  23 #include "cpu/x86/mtrr/earlymtrr.c"
  24 #include "cpu/x86/bist.h"
  25 #include "northbridge/amd/amdk8/setup_resource_map.c"
  26 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 static void memreset_setup(void)
  31 {
  32    if (is_cpu_pre_c0())
  33         outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  34    else
  35         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  36    outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  37 }
  38
  39 static void memreset(int controllers, const struct mem_controller *ctrl)
  40 {
  41    if (is_cpu_pre_c0()) {
  42         udelay(800);
  43         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  44         udelay(90);
  45    }
  46 }
  47
  48 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  49
  50 static inline int spd_read_byte(unsigned device, unsigned address)
  51 {
  52         return smbus_read_byte(device, address);
  53 }
  54
  55 #include "northbridge/amd/amdk8/raminit.c"
  56 #include "northbridge/amd/amdk8/resourcemap.c"
  57 #include "northbridge/amd/amdk8/coherent_ht.c"
  58 #include "lib/generic_sdram.c"
  59 #include "cpu/amd/dualcore/dualcore.c"
  60 #include "cpu/amd/car/post_cache_as_ram.c"
  61 #include "cpu/amd/model_fxx/init_cpus.c"
  62 #include "northbridge/amd/amdk8/early_ht.c"
  63
  64 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  65 {
  66         static const struct mem_controller cpu[] = {
  67                 {
  68                         .node_id = 0,
  69                         .f0 = PCI_DEV(0, 0x18, 0),
  70                         .f1 = PCI_DEV(0, 0x18, 1),
  71                         .f2 = PCI_DEV(0, 0x18, 2),
  72                         .f3 = PCI_DEV(0, 0x18, 3),
  73                         .channel0 = { DIMM0, DIMM2, 0, 0 },
  74                         .channel1 = { DIMM1, DIMM3, 0, 0 },
  75                 },
  76         };
  77
  78         int needs_reset;
  79
  80         if (!cpu_init_detectedx && boot_cpu()) {
  81                 /* Nothing special needs to be done to find bus 0 */
  82                 /* Allow the HT devices to be found */
  83                 enumerate_ht_chain();
  84         }
  85
  86         if (bist == 0)
  87                 init_cpus(cpu_init_detectedx);
  88
  89 //      post_code(0x32);
  90
  91         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  92         uart_init();
  93         console_init();
  94
  95         /* Halt if there was a built in self test failure */
  96         report_bist_failure(bist);
  97
  98         setup_default_resource_map();
  99
 100         needs_reset = setup_coherent_ht_domain();
 101
 102 #if CONFIG_LOGICAL_CPUS==1
 103         // It is said that we should start core1 after all core0 launched
 104         start_other_cores();
 105 #endif
 106         needs_reset |= ht_setup_chains_x();
 107
 108         if (needs_reset) {
 109                 print_info("ht reset -\n");
 110                 soft_reset();
 111         }
 112
 113         enable_smbus();
 114
 115         memreset_setup();
 116         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 117
 118         post_cache_as_ram();
 119 }