src/mainboard/tyan/s2850/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11 #include <lib.h>
  12 #include <spd.h>
  13 #include <cpu/amd/model_fxx_rev.h>
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  23 #include "cpu/x86/mtrr/earlymtrr.c"
  24 #include "cpu/x86/bist.h"
  25 #include "northbridge/amd/amdk8/setup_resource_map.c"
  26 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 static void memreset_setup(void)
  31 {
  32    if (is_cpu_pre_c0()) {
  33         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  34    }
  35    else {
  36         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  37    }
  38         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  39 }
  40
  41 static void memreset(int controllers, const struct mem_controller *ctrl)
  42 {
  43    if (is_cpu_pre_c0()) {
  44         udelay(800);
  45         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  46         udelay(90);
  47    }
  48 }
  49
  50 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  51 {
  52         /* nothing to do */
  53 }
  54
  55 static inline int spd_read_byte(unsigned device, unsigned address)
  56 {
  57         return smbus_read_byte(device, address);
  58 }
  59
  60 #include "northbridge/amd/amdk8/raminit.c"
  61 #include "northbridge/amd/amdk8/resourcemap.c"
  62 #include "northbridge/amd/amdk8/coherent_ht.c"
  63 #include "lib/generic_sdram.c"
  64 #include "cpu/amd/dualcore/dualcore.c"
  65 #include "cpu/amd/car/post_cache_as_ram.c"
  66 #include "cpu/amd/model_fxx/init_cpus.c"
  67 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  68 #include "northbridge/amd/amdk8/early_ht.c"
  69
  70 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  71 {
  72         static const struct mem_controller cpu[] = {
  73                 {
  74                         .node_id = 0,
  75                         .f0 = PCI_DEV(0, 0x18, 0),
  76                         .f1 = PCI_DEV(0, 0x18, 1),
  77                         .f2 = PCI_DEV(0, 0x18, 2),
  78                         .f3 = PCI_DEV(0, 0x18, 3),
  79                         .channel0 = { DIMM0, DIMM2, 0, 0 },
  80                         .channel1 = { DIMM1, DIMM3, 0, 0 },
  81                 },
  82         };
  83
  84         int needs_reset;
  85
  86         if (!cpu_init_detectedx && boot_cpu()) {
  87                 /* Nothing special needs to be done to find bus 0 */
  88                 /* Allow the HT devices to be found */
  89
  90                 enumerate_ht_chain();
  91
  92                 /* Setup the amd8111 */
  93                 amd8111_enable_rom();
  94         }
  95
  96         if (bist == 0) {
  97                 init_cpus(cpu_init_detectedx);
  98         }
  99
 100 //      post_code(0x32);
 101
 102         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 103         uart_init();
 104         console_init();
 105
 106         /* Halt if there was a built in self test failure */
 107         report_bist_failure(bist);
 108
 109         setup_default_resource_map();
 110
 111         needs_reset = setup_coherent_ht_domain();
 112
 113 #if CONFIG_LOGICAL_CPUS==1
 114         // It is said that we should start core1 after all core0 launched
 115         start_other_cores();
 116 #endif
 117         needs_reset |= ht_setup_chains_x();
 118
 119         if (needs_reset) {
 120                 print_info("ht reset -\n");
 121                 soft_reset();
 122         }
 123
 124         enable_smbus();
 125
 126         memreset_setup();
 127         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 128
 129         post_cache_as_ram();
 130 }
 131