src/mainboard/tyan/s2850/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11 #include <lib.h>
  12 #include <spd.h>
  13
  14 #include <cpu/amd/model_fxx_rev.h>
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25
  26 #include "cpu/x86/mtrr/earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #include "northbridge/amd/amdk8/setup_resource_map.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  34
  35 static void memreset_setup(void)
  36 {
  37    if (is_cpu_pre_c0()) {
  38         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  39    }
  40    else {
  41         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  42    }
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48    if (is_cpu_pre_c0()) {
  49         udelay(800);
  50         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  51         udelay(90);
  52    }
  53 }
  54
  55 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  56 {
  57         /* nothing to do */
  58 }
  59
  60 static inline int spd_read_byte(unsigned device, unsigned address)
  61 {
  62         return smbus_read_byte(device, address);
  63 }
  64
  65 #include "northbridge/amd/amdk8/raminit.c"
  66 #include "northbridge/amd/amdk8/resourcemap.c"
  67 #include "northbridge/amd/amdk8/coherent_ht.c"
  68 #include "lib/generic_sdram.c"
  69
  70 #include "cpu/amd/dualcore/dualcore.c"
  71
  72
  73
  74 #include "cpu/amd/car/post_cache_as_ram.c"
  75
  76 #include "cpu/amd/model_fxx/init_cpus.c"
  77
  78 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  79 #include "northbridge/amd/amdk8/early_ht.c"
  80
  81 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  82 {
  83         static const struct mem_controller cpu[] = {
  84                 {
  85                         .node_id = 0,
  86                         .f0 = PCI_DEV(0, 0x18, 0),
  87                         .f1 = PCI_DEV(0, 0x18, 1),
  88                         .f2 = PCI_DEV(0, 0x18, 2),
  89                         .f3 = PCI_DEV(0, 0x18, 3),
  90                         .channel0 = { DIMM0, DIMM2, 0, 0 },
  91                         .channel1 = { DIMM1, DIMM3, 0, 0 },
  92                 },
  93         };
  94
  95         int needs_reset;
  96
  97         if (!cpu_init_detectedx && boot_cpu()) {
  98                 /* Nothing special needs to be done to find bus 0 */
  99                 /* Allow the HT devices to be found */
 100
 101                 enumerate_ht_chain();
 102
 103                 /* Setup the amd8111 */
 104                 amd8111_enable_rom();
 105         }
 106
 107         if (bist == 0) {
 108                 init_cpus(cpu_init_detectedx);
 109         }
 110
 111 //      post_code(0x32);
 112
 113         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 114         uart_init();
 115         console_init();
 116
 117         /* Halt if there was a built in self test failure */
 118         report_bist_failure(bist);
 119
 120         setup_default_resource_map();
 121
 122         needs_reset = setup_coherent_ht_domain();
 123
 124 #if CONFIG_LOGICAL_CPUS==1
 125         // It is said that we should start core1 after all core0 launched
 126         start_other_cores();
 127 #endif
 128         needs_reset |= ht_setup_chains_x();
 129
 130         if (needs_reset) {
 131                 print_info("ht reset -\n");
 132                 soft_reset();
 133         }
 134
 135         enable_smbus();
 136
 137         memreset_setup();
 138         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 139
 140         post_cache_as_ram();
 141 }
 142