1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_IRQ_SLOT_COUNT
8 uses CONFIG_HAVE_OPTION_TABLE
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
14 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_IMAGE_SIZE
18 uses CONFIG_ROM_SECTION_SIZE
19 uses CONFIG_ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
24 uses CONFIG_PAYLOAD_SIZE
26 uses CONFIG_XIP_ROM_SIZE
27 uses CONFIG_XIP_ROM_BASE
28 uses CONFIG_STACK_SIZE
30 uses CONFIG_USE_OPTION_TABLE
31 uses CONFIG_LB_CKS_RANGE_START
32 uses CONFIG_LB_CKS_RANGE_END
33 uses CONFIG_LB_CKS_LOC
34 uses CONFIG_MAINBOARD_PART_NUMBER
35 uses CONFIG_MAINBOARD_VENDOR
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
38 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
39 uses COREBOOT_EXTRA_VERSION
41 uses CONFIG_TTYS0_BAUD
42 uses CONFIG_TTYS0_BASE
44 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
45 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
46 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_SERIAL8250
48 uses CONFIG_HAVE_INIT_TIMER
51 uses CONFIG_CROSS_COMPILE
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses CONFIG_HW_MEM_HOLE_SIZEK
59 uses CONFIG_USE_DCACHE_RAM
60 uses CONFIG_DCACHE_RAM_BASE
61 uses CONFIG_DCACHE_RAM_SIZE
63 uses CONFIG_USE_PRINTK_IN_CAR
70 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
72 default CONFIG_ROM_SIZE=524288
75 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
77 #default CONFIG_FALLBACK_SIZE=131072
79 default CONFIG_FALLBACK_SIZE=0x40000
82 ## Build code for the fallback boot
84 default CONFIG_HAVE_FALLBACK_BOOT=1
87 ## Build code to reset the motherboard from coreboot
89 default CONFIG_HAVE_HARD_RESET=1
92 ## Build code to export a programmable irq routing table
94 default CONFIG_HAVE_PIRQ_TABLE=1
95 default CONFIG_IRQ_SLOT_COUNT=12
98 ## Build code to export an x86 MP table
99 ## Useful for specifying IRQ routing values
101 default CONFIG_HAVE_MP_TABLE=1
104 ## Build code to export a CMOS option table
106 default CONFIG_HAVE_OPTION_TABLE=1
109 ## Move the default coreboot cmos range off of AMD RTC registers
111 default CONFIG_LB_CKS_RANGE_START=49
112 default CONFIG_LB_CKS_RANGE_END=122
113 default CONFIG_LB_CKS_LOC=123
116 ## Build code for SMP support
117 ## Only worry about 2 micro processors
120 default CONFIG_MAX_CPUS=2
121 default CONFIG_MAX_PHYSICAL_CPUS=1
122 default CONFIG_LOGICAL_CPUS=1
125 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
128 default CONFIG_CONSOLE_VGA=1
129 default CONFIG_PCI_ROM_RUN=1
133 ## enable CACHE_AS_RAM specifics
135 default CONFIG_USE_DCACHE_RAM=1
136 default CONFIG_DCACHE_RAM_BASE=0xcf000
137 default CONFIG_DCACHE_RAM_SIZE=0x1000
138 default CONFIG_USE_INIT=0
141 ## Build code to setup a generic IOAPIC
143 default CONFIG_IOAPIC=1
146 ## Clean up the motherboard id strings
148 default CONFIG_MAINBOARD_PART_NUMBER="S2850"
149 default CONFIG_MAINBOARD_VENDOR="Tyan"
150 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
151 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850
154 ### coreboot layout values
157 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
158 default CONFIG_ROM_IMAGE_SIZE = 65536
161 ## Use a small 8K stack
163 default CONFIG_STACK_SIZE=0x2000
166 ## Use a small 16K heap
168 default CONFIG_HEAP_SIZE=0x4000
171 ## Only use the option table in a normal image
173 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
176 ## Coreboot C code runs at this location in RAM
178 default CONFIG_RAMBASE=0x00004000
181 ## Load the payload from the ROM
183 default CONFIG_ROM_PAYLOAD = 1
186 ### Defaults of options that you may want to override in the target config file
190 ## The default compiler
192 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
196 ## Disable the gdb stub by default
198 default CONFIG_GDB_STUB=0
200 default CONFIG_USE_PRINTK_IN_CAR=1
203 ## The Serial Console
206 # To Enable the Serial Console
207 default CONFIG_CONSOLE_SERIAL8250=1
209 ## Select the serial console baud rate
210 default CONFIG_TTYS0_BAUD=115200
211 #default CONFIG_TTYS0_BAUD=57600
212 #default CONFIG_TTYS0_BAUD=38400
213 #default CONFIG_TTYS0_BAUD=19200
214 #default CONFIG_TTYS0_BAUD=9600
215 #default CONFIG_TTYS0_BAUD=4800
216 #default CONFIG_TTYS0_BAUD=2400
217 #default CONFIG_TTYS0_BAUD=1200
219 # Select the serial console base port
220 default CONFIG_TTYS0_BASE=0x3f8
222 # Select the serial protocol
223 # This defaults to 8 data bits, 1 stop bit, and no parity
224 default CONFIG_TTYS0_LCS=0x3
227 ### Select the coreboot loglevel
229 ## EMERG 1 system is unusable
230 ## ALERT 2 action must be taken immediately
231 ## CRIT 3 critical conditions
232 ## ERR 4 error conditions
233 ## WARNING 5 warning conditions
234 ## NOTICE 6 normal but significant condition
235 ## INFO 7 informational
236 ## CONFIG_DEBUG 8 debug-level messages
237 ## SPEW 9 Way too many details
239 ## Request this level of debugging output
240 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
241 ## At a maximum only compile in this level of debugging
242 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
245 ## Select power on after power fail setting
246 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
253 default CONFIG_CBFS=0