4 #include <device/pci_def.h>
6 #include <device/pnp_def.h>
7 #include <arch/romcc_io.h>
8 #include <cpu/x86/lapic.h>
9 #include "option_table.h"
10 #include "pc80/mc146818rtc_early.c"
11 #include "pc80/serial.c"
12 #include "console/console.c"
13 #include "lib/ramtest.c"
15 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
16 #include "northbridge/intel/e7501/raminit.h"
18 #include "northbridge/intel/e7501/debug.c"
19 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
21 #include "cpu/x86/mtrr/earlymtrr.c"
22 #include "cpu/x86/bist.h"
24 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
26 // FIXME: There's another hard_reset() in reset.c. Why?
27 static void hard_reset(void)
34 static inline int spd_read_byte(unsigned device, unsigned address)
36 return smbus_read_byte(device, address);
39 #include "northbridge/intel/e7501/raminit.c"
40 #include "northbridge/intel/e7501/reset_test.c"
41 #include "lib/generic_sdram.c"
43 void main(unsigned long bist)
45 static const struct mem_controller memctrl[] = {
47 .d0 = PCI_DEV(0, 0, 0),
48 .d0f1 = PCI_DEV(0, 0, 1),
49 .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
50 .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
58 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
62 /* Halt if there was a built in self test failure */
63 report_bist_failure(bist);
65 if(bios_reset_detected()) {
71 dump_spd_registers(&memctrl[0]);
74 dump_smbus_registers();
77 sdram_initialize(1, memctrl);
84 dump_pci_device(PCI_DEV(0, 0, 0));