6 #include <device/pci_def.h>
8 #include <device/pnp_def.h>
9 #include <arch/romcc_io.h>
10 #include <cpu/x86/lapic.h>
11 #include "option_table.h"
12 #include "pc80/mc146818rtc_early.c"
13 #include "pc80/serial.c"
14 #include "arch/i386/lib/console.c"
15 #include "lib/ramtest.c"
18 static void post_code(uint8_t value) {
21 for(i=0;i<0x80000;i++) {
28 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
29 #include "northbridge/intel/e7501/raminit.h"
31 #include "cpu/x86/lapic/boot_cpu.c"
32 #include "northbridge/intel/e7501/debug.c"
33 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
35 #include "cpu/x86/mtrr/earlymtrr.c"
36 #include "cpu/x86/bist.h"
38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
40 // FIXME: There's another hard_reset() in reset.c. Why?
41 static void hard_reset(void)
48 static void soft_reset(void)
57 static void memreset_setup(void)
61 static void memreset(int controllers, const struct mem_controller *ctrl)
65 static inline void activate_spd_rom(const struct mem_controller *ctrl)
70 static inline int spd_read_byte(unsigned device, unsigned address)
72 return smbus_read_byte(device, address);
76 #include "northbridge/intel/e7501/raminit.c"
77 #include "northbridge/intel/e7501/reset_test.c"
78 #include "lib/generic_sdram.c"
81 #include "cpu/x86/car/copy_and_run.c"
83 void amd64_main(unsigned long bist)
85 static const struct mem_controller memctrl[] = {
87 .d0 = PCI_DEV(0, 0, 0),
88 .d0f1 = PCI_DEV(0, 0, 1),
89 .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
90 .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
94 unsigned cpu_reset = 0;
105 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
109 /* Halt if there was a built in self test failure */
110 report_bist_failure(bist);
112 // setup_s2735_resource_map();
114 if(bios_reset_detected()) {
121 dump_spd_registers(&memctrl[0]);
124 dump_smbus_registers();
128 sdram_initialize(1, memctrl);
135 dump_pci_device(PCI_DEV(0, 0, 0));
141 /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
148 printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
150 print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
160 printk(BIOS_DEBUG, "cpu_reset = %08x\r\n",cpu_reset);
162 print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
166 print_debug("Clearing initial memory region: ");
168 print_debug("No cache as ram now - ");
170 /* store cpu_reset to ebx */
177 #define CLEAR_FIRST_1M_RAM 1
178 #include "cpu/x86/car/cache_as_ram_post.c"
181 #undef CLEAR_FIRST_1M_RAM
182 #include "cpu/x86/car/cache_as_ram_post.c"
186 /* set new esp */ /* before CONFIG_RAMBASE */
189 ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
193 unsigned new_cpu_reset;
195 /* get back cpu_reset from ebx */
198 :"=a" (new_cpu_reset)
201 /* We can not go back any more, we lost old stack data in cache as ram*/
202 if(new_cpu_reset==0) {
203 print_debug("Use Ram as Stack now - done\r\n");
206 print_debug("Use Ram as Stack now - \r\n");
209 printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
211 print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
214 #ifdef DEACTIVATE_CAR
215 print_debug("Deactivating CAR");
216 #include DEACTIVATE_CAR_FILE
217 print_debug(" - Done.\r\n");
219 /*copy and execute coreboot_ram */
220 copy_and_run(new_cpu_reset);
221 /* We will not return */
226 print_debug("should not be here -\r\n");