src/mainboard/tyan/s2735/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #include <stdint.h>
   5 #include <string.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "lib/ramtest.c"
  16
  17 #if 0
  18 static void post_code(uint8_t value) {
  19 #if 1
  20         int i;
  21         for(i=0;i<0x80000;i++) {
  22                 outb(value, 0x80);
  23         }
  24 #endif
  25 }
  26 #endif
  27
  28 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
  29 #include "northbridge/intel/e7501/raminit.h"
  30
  31 #include "cpu/x86/lapic/boot_cpu.c"
  32 #include "northbridge/intel/e7501/debug.c"
  33 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  34
  35 #include "cpu/x86/mtrr/earlymtrr.c"
  36 #include "cpu/x86/bist.h"
  37
  38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  39
  40 // FIXME: There's another hard_reset() in reset.c. Why?
  41 static void hard_reset(void)
  42 {
  43         /* full reset */
  44         outb(0x0a, 0x0cf9);
  45         outb(0x0e, 0x0cf9);
  46 }
  47
  48 static void soft_reset(void)
  49 {
  50 #if 1
  51         /* link reset */
  52         outb(0x02, 0x0cf9);
  53         outb(0x06, 0x0cf9);
  54 #endif
  55 }
  56
  57 static void memreset_setup(void)
  58 {
  59 }
  60
  61 static void memreset(int controllers, const struct mem_controller *ctrl)
  62 {
  63 }
  64
  65 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  66 {
  67         /* nothing to do */
  68 }
  69
  70 static inline int spd_read_byte(unsigned device, unsigned address)
  71 {
  72         return smbus_read_byte(device, address);
  73 }
  74
  75
  76 #include "northbridge/intel/e7501/raminit.c"
  77 #include "northbridge/intel/e7501/reset_test.c"
  78 #include "lib/generic_sdram.c"
  79
  80
  81 #include "cpu/x86/car/copy_and_run.c"
  82
  83 #if CONFIG_USE_FALLBACK_IMAGE == 1
  84
  85 #include "southbridge/intel/i82801er/cmos_failover.c"
  86
  87 void real_main(unsigned long bist);
  88
  89 void amd64_main(unsigned long bist)
  90 {
  91         /* Is this a deliberate reset by the bios */
  92 //        post_code(0x22);
  93         if (bios_reset_detected() && last_boot_normal()) {
  94                 goto normal_image;
  95         }
  96         /* This is the primary cpu how should I boot? */
  97         else {
  98                 check_cmos_failed();
  99                 if (do_normal_boot()) {
 100                         goto normal_image;
 101                 }
 102                 else {
 103                         goto fallback_image;
 104                 }
 105         }
 106  normal_image:
 107 //        post_code(0x23);
 108         __asm__ volatile ("jmp __normal_image"
 109                 : /* outputs */
 110                 : "a" (bist) /* inputs */
 111                 );
 112  cpu_reset:
 113 //        post_code(0x24);
 114 #if 0
 115         //CPU reset will reset memtroller ???
 116         asm volatile ("jmp __cpu_reset"
 117                 : /* outputs */
 118                 : "a"(bist) /* inputs */
 119                 );
 120 #endif
 121
 122  fallback_image:
 123 //        post_code(0x25);
 124         real_main(bist);
 125 }
 126 void real_main(unsigned long bist)
 127 #else
 128 void amd64_main(unsigned long bist)
 129 #endif
 130 {
 131         static const struct mem_controller memctrl[] = {
 132                 {
 133                         .d0 = PCI_DEV(0, 0, 0),
 134                         .d0f1 = PCI_DEV(0, 0, 1),
 135                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
 136                         .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
 137                 },
 138         };
 139
 140         unsigned cpu_reset = 0;
 141
 142        if (bist == 0)
 143         {
 144 //              early_mtrr_init();
 145                 enable_lapic();
 146
 147         }
 148
 149 //      post_code(0x32);
 150
 151         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 152         uart_init();
 153         console_init();
 154
 155         /* Halt if there was a built in self test failure */
 156         report_bist_failure(bist);
 157
 158 //        setup_s2735_resource_map();
 159
 160         if(bios_reset_detected()) {
 161                 cpu_reset = 1;
 162                 goto cpu_reset_x;
 163         }
 164
 165         enable_smbus();
 166 #if 0
 167         dump_spd_registers(&memctrl[0]);
 168 #endif
 169 #if 0
 170         dump_smbus_registers();
 171 #endif
 172
 173         memreset_setup();
 174         sdram_initialize(1, memctrl);
 175
 176 #if 0
 177         dump_pci_devices();
 178 #endif
 179
 180 #if 1
 181         dump_pci_device(PCI_DEV(0, 0, 0));
 182 #endif
 183
 184
 185 #if 1
 186         {
 187                 /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
 188                 unsigned v_esp;
 189                 __asm__ volatile (
 190                         "movl   %%esp, %0\n\t"
 191                         : "=a" (v_esp)
 192                 );
 193 #if CONFIG_USE_INIT
 194                 printk_debug("v_esp=%08x\r\n", v_esp);
 195 #else
 196                 print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
 197 #endif
 198         }
 199
 200 #endif
 201 #if 1
 202
 203 cpu_reset_x:
 204
 205 #if CONFIG_USE_INIT
 206         printk_debug("cpu_reset = %08x\r\n",cpu_reset);
 207 #else
 208         print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
 209 #endif
 210
 211         if(cpu_reset == 0) {
 212                 print_debug("Clearing initial memory region: ");
 213         }
 214         print_debug("No cache as ram now - ");
 215
 216         /* store cpu_reset to ebx */
 217         __asm__ volatile (
 218                 "movl %0, %%ebx\n\t"
 219                 ::"a" (cpu_reset)
 220         );
 221
 222         if(cpu_reset==0) {
 223 #define CLEAR_FIRST_1M_RAM 1
 224 #include "cpu/x86/car/cache_as_ram_post.c"
 225         }
 226         else {
 227 #undef CLEAR_FIRST_1M_RAM
 228 #include "cpu/x86/car/cache_as_ram_post.c"
 229         }
 230
 231         __asm__ volatile (
 232                 /* set new esp */ /* before CONFIG_RAMBASE */
 233                 "subl   %0, %%ebp\n\t"
 234                 "subl   %0, %%esp\n\t"
 235                 ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
 236         );
 237
 238         {
 239                 unsigned new_cpu_reset;
 240
 241                 /* get back cpu_reset from ebx */
 242                 __asm__ volatile (
 243                         "movl %%ebx, %0\n\t"
 244                         :"=a" (new_cpu_reset)
 245                 );
 246
 247                 /* We can not go back any more, we lost old stack data in cache as ram*/
 248                 if(new_cpu_reset==0) {
 249                         print_debug("Use Ram as Stack now - done\r\n");
 250                 } else
 251                 {
 252                         print_debug("Use Ram as Stack now - \r\n");
 253                 }
 254 #if CONFIG_USE_INIT
 255                 printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
 256 #else
 257                 print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
 258 #endif
 259
 260 #ifdef DEACTIVATE_CAR
 261                 print_debug("Deactivating CAR");
 262 #include DEACTIVATE_CAR_FILE
 263                 print_debug(" - Done.\r\n");
 264 #endif
 265                 /*copy and execute coreboot_ram */
 266                 copy_and_run(new_cpu_reset);
 267                 /* We will not return */
 268         }
 269 #endif
 270
 271
 272         print_debug("should not be here -\r\n");
 273
 274 }